mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-14 10:09:41 +00:00
8763bbf6cf
* WIP POC of dispatcher
* Dispatcher python workflow setup.
* Dispatcher cleanup and updates.
Further dispatcher cleanup and updates.
Build fixes
Improvements and python to CK example
Improvements to readme
* Fixes to python paths
* Cleaning up code
* Improving dispatcher support for different arch
Fixing typos
* Fix formatting errors
* Cleaning up examples
* Improving codegeneration
* Improving and fixing C++ examples
* Adding conv functionality (fwd,bwd,bwdw) and examples.
* Fixes based on feedback.
* Further fixes based on feedback.
* Adding stress test for autogeneration and autocorrection, and fixing preshuffle bug.
* Another round of improvements based on feedback.
* Trimming out unnecessary code.
* Fixing the multi-D implementation.
* Using gpu verification for gemms and fixing convolutions tflops calculation.
* Fix counter usage issue and arch filtering per ops.
* Adding changelog and other fixes.
* Improve examples and resolve critical bugs.
* Reduce build time for python examples.
* Fixing minor bug.
* Fix compilation error.
* Improve installation instructions for dispatcher.
* Add docker based installation instructions for dispatcher.
* Fixing arch-based filtering to match tile engine.
* Remove dead code and fix arch filtering.
* Minor bugfix.
* Updates after rebase.
* Trimming code.
* Fix copyright headers.
* Consolidate examples, cut down code.
* Minor fixes.
* Improving python examples.
* Update readmes.
* Remove conv functionality.
* Cleanup following conv removable.
[ROCm/composable_kernel commit: 9e049a32a1]
271 lines
9.3 KiB
JSON
271 lines
9.3 KiB
JSON
{
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"_comment": "Single source of truth for GPU architecture specifications. Edit this file to add new GPU support.",
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"_version": "1.2.0",
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"_instructions": "See ADDING_NEW_GPU.md for instructions on adding new GPU support.",
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"_supported_arch_note": "CK Tile supports: GFX9 (gfx908, gfx90a, gfx942, gfx950), GFX10.3 (gfx103x), GFX11 (gfx110x, gfx115x), GFX12 (gfx120x)",
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"architectures": {
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"gfx908": {
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"family": "cdna1",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI100",
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"warp_size": 64,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]]
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}
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},
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"gfx90a": {
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"family": "cdna2",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI200 series",
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"warp_size": 64,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]]
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}
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},
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"gfx942": {
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"family": "cdna3",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI300 series",
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"warp_size": 64,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64]],
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"fp8_bf8_fp32": [[32, 32, 16], [16, 16, 32], [32, 32, 32]],
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"bf8_fp8_fp32": [[32, 32, 16]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]]
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}
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},
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"gfx950": {
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"family": "cdna4",
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"target_family": "gfx9",
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"architecture": "cdna",
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"description": "AMD Instinct MI350 series",
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"warp_size": 64,
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"lds_capacity_kb": 160,
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"warp_configs": [
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[1, 4, 1],
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[2, 2, 1],
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[4, 1, 1]
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],
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"warp_tile_combos": {
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"fp32_fp32_fp32": [[16, 16, 4], [16, 16, 16]],
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [4, 64, 16], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64], [16, 16, 128], [32, 32, 64]],
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"fp8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 128], [32, 32, 64]],
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"bf8_fp8_fp32": [[32, 32, 16], [16, 16, 128], [32, 32, 64]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64], [16, 16, 128], [32, 32, 64]],
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"int8_int8_int32": [[32, 32, 16], [16, 16, 32]],
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"pk_fp4_pk_fp4_fp32": [[16, 16, 128]]
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}
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},
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"gfx1100": {
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"family": "rdna3",
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"target_family": "gfx11",
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"architecture": "rdna",
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"description": "AMD Radeon RX 7900 series (RDNA3)",
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"warp_size": 32,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[2, 4, 1],
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[1, 8, 1],
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[8, 1, 1],
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[4, 2, 1]
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],
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"warp_tile_combos": {
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"fp16_fp16_fp32": [[16, 16, 16]],
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"bf16_bf16_fp32": [[16, 16, 16]],
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"int8_int8_int32": [[16, 16, 16]]
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}
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},
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"gfx1200": {
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"family": "rdna4",
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"target_family": "gfx12",
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"architecture": "rdna",
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"description": "AMD Radeon RX 9000 series (RDNA4)",
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"warp_size": 32,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[2, 4, 1],
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[1, 8, 1],
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[8, 1, 1],
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[4, 2, 1]
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],
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"warp_tile_combos": {
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"fp16_fp16_fp32": [[16, 16, 16]],
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"bf16_bf16_fp32": [[16, 16, 16]],
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"fp8_fp8_fp32": [[16, 16, 16]],
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"bf8_bf8_fp32": [[16, 16, 16]],
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"fp8_bf8_fp32": [[16, 16, 16]],
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"bf8_fp8_fp32": [[16, 16, 16]],
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"int8_int8_int32": [[16, 16, 16]]
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}
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},
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"gfx1201": {
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"family": "rdna4",
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"target_family": "gfx12",
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"architecture": "rdna",
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"description": "AMD Radeon RX 9000 series (RDNA4)",
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"warp_size": 32,
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"lds_capacity_kb": 64,
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"warp_configs": [
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[2, 4, 1],
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[1, 8, 1],
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[8, 1, 1],
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[4, 2, 1]
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],
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"warp_tile_combos": {
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"fp16_fp16_fp32": [[16, 16, 16]],
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"bf16_bf16_fp32": [[16, 16, 16]],
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"fp8_fp8_fp32": [[16, 16, 16]],
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"bf8_bf8_fp32": [[16, 16, 16]],
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"fp8_bf8_fp32": [[16, 16, 16]],
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"bf8_fp8_fp32": [[16, 16, 16]],
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"int8_int8_int32": [[16, 16, 16]]
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}
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}
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},
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"element_sizes": {
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"fp16": 2,
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"bf16": 2,
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"fp32": 4,
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"fp64": 8,
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"fp8": 1,
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"bf8": 1,
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"int8": 1,
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"int4": 0.5,
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"pk_fp4": 0.5,
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"int32": 4
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},
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"datatype_cpp_map": {
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"_comment": "Maps dtype string to CK Tile C++ type for code generation",
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"fp16": "ck_tile::half_t",
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"bf16": "ck_tile::bf16_t",
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"fp32": "float",
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"fp64": "double",
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"fp8": "ck_tile::fp8_t",
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"bf8": "ck_tile::bf8_t",
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"int8": "ck_tile::int8_t",
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"int4": "ck_tile::pk_int4_t",
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"pk_fp4": "ck_tile::pk_fp4_t",
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"int32": "ck_tile::int32_t"
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},
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"dtype_combinations": {
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"_comment": "All valid (A, B) -> Acc combinations for GEMM from warp_gemm_dispatcher.hpp",
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"fp32_fp32": {"acc": "fp32", "notes": "Full precision"},
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"fp16_fp16": {"acc": "fp32", "notes": "Standard half precision"},
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"bf16_bf16": {"acc": "fp32", "notes": "Brain float 16"},
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"fp8_fp8": {"acc": "fp32", "notes": "FP8 E4M3"},
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"fp8_bf8": {"acc": "fp32", "notes": "Mixed FP8/BF8"},
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"bf8_fp8": {"acc": "fp32", "notes": "Mixed BF8/FP8"},
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"bf8_bf8": {"acc": "fp32", "notes": "BF8 E5M2"},
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"int8_int8": {"acc": "int32", "notes": "Integer GEMM"},
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"pk_fp4_pk_fp4": {"acc": "fp32", "notes": "Packed 4-bit float"}
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},
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"layout_cpp_map": {
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"_comment": "Maps layout character to CK Tile C++ type",
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"r": "ck_tile::tensor_layout::gemm::RowMajor",
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"c": "ck_tile::tensor_layout::gemm::ColumnMajor"
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},
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"pipeline_lds_limits": {
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"_comment": "LDS capacity limits in bytes for different pipeline types",
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"mem": 65536,
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"compv1": 65536,
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"compv2": 65536,
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"compv3": 65536,
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"compv4": 32768,
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"compv5": 65536,
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"preshufflev1": 32768,
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"preshufflev2": 32768,
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"default": 65536
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},
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"unsupported_trait_combos": {
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"_comment": "Only 'mem' pipeline supports interwave scheduler. All compute pipelines only support intrawave.",
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"combinations": [
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["compv3", "cshuffle", "interwave"],
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["compv3", "default", "interwave"],
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["compv4", "cshuffle", "interwave"],
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["compv4", "default", "interwave"],
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["compv5", "cshuffle", "interwave"],
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["compv5", "default", "interwave"],
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["compv6", "cshuffle", "interwave"],
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["compv6", "default", "interwave"],
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["comp_async", "cshuffle", "interwave"],
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["comp_async", "default", "interwave"]
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]
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},
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"preshuffle_warp_tile_combos": {
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"_comment": "Preshuffle-specific warp tile combinations (subset of standard GEMM, no [4, 64, 16])",
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"gfx90a": {
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32]]
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},
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"gfx942": {
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 64], [16, 16, 32]],
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"int8_int8_int32": [[16, 16, 32], [32, 32, 16]]
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},
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"gfx950": {
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"fp16_fp16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"bf16_bf16_fp32": [[32, 32, 8], [16, 16, 16], [32, 32, 16], [16, 16, 32], [64, 4, 16]],
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"fp8_fp8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 32], [16, 16, 64], [16, 16, 128], [32, 32, 64]],
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"bf8_bf8_fp32": [[32, 32, 16], [32, 32, 32], [16, 16, 64], [16, 16, 32], [16, 16, 128], [32, 32, 64]]
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}
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},
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"preshuffle_pipelines": {
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"_comment": "Pipelines supported for preshuffle GEMM variant",
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"supported": ["preshufflev2"]
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}
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}
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