mirror of
https://github.com/ROCm/composable_kernel.git
synced 2026-05-11 08:50:17 +00:00
de37550f72
* reopen masking att instance due to CI is upgraded * re-enable instances previously failed on 9110 * enable ksize-kpadding pair validity test * add non-masked attention+permute test; expose masking boolean to attention kernel handles * disable bench * fix test * move files * bulk rename batched_gemm_masking_scale_softmax_gemm_permute to batched_gemm_softmax_gemm_permute * format * amend rename * disable bench in test * add mask/no-mask test for non-permute attention kernels * disable broken kernel instance * example working add non-permuted problem statement evaluating whether overhead comes from permutation or the extra kernel arg * interface for bias addition without implementing it * test and profiler running * tidy * mask type determined by enum class * unify example code * move masking specialization to its own header * align formats * extract helper functions * experiment merging dims for attn w/ permute; shows perf parity with attn wo/ permute * add tensor specialization to template args since tensor spec packed shows perf parity when permutation isn't needed remove redundant template args comment on 'packed' tensor specialization * grouped attention with input/output permute example * format * clean up * refactor acc0 tile visitor Co-authored-by: shaojiewang <wsjmessi@163.com> Co-authored-by: Chao Liu <chao.liu2@amd.com>
196 lines
6.7 KiB
C++
196 lines
6.7 KiB
C++
// SPDX-License-Identifier: MIT
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// Copyright (c) 2018-2022, Advanced Micro Devices, Inc. All rights reserved.
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#pragma once
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#ifndef CK_DONT_USE_HIP_RUNTIME_HEADERS
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#include "hip/hip_runtime.h"
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#include "hip/hip_fp16.h"
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#endif
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#define CK_TIME_KERNEL 1
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// constant address space for kernel parameter
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// https://llvm.org/docs/AMDGPUUsage.html#address-spaces
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#define CK_CONSTANT_ADDRESS_SPACE __attribute__((address_space(4)))
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// launch bounds
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#define CK_USE_LAUNCH_BOUNDS 1
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#ifdef CK_USE_LAUNCH_BOUNDS
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#define CK_MAX_THREAD_PER_BLOCK 256
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#define CK_MIN_BLOCK_PER_CU 2
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#endif
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// check GPU target
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#ifdef __HIP_DEVICE_COMPILE__
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#if !(defined(__gfx803__) || defined(__gfx900__) || defined(__gfx906__) || defined(__gfx908__) || \
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defined(__gfx90a__) || defined(__gfx1030__))
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#error Not supported target
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#endif
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#endif
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// buffer resource
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#ifndef __HIP_DEVICE_COMPILE__ // for host code
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#define CK_BUFFER_RESOURCE_3RD_DWORD -1
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#elif defined(__gfx803__) || defined(__gfx900__) || defined(__gfx906__) || defined(__gfx908__) || \
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defined(__gfx90a__) // for GPU code
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#define CK_BUFFER_RESOURCE_3RD_DWORD 0x00020000
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#elif defined(__gfx1030__) // for GPU code
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#define CK_BUFFER_RESOURCE_3RD_DWORD 0x31014000
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#endif
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// FMA instruction
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#ifndef __HIP_DEVICE_COMPILE__ // for host code, define nothing
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#elif defined(__gfx803__) || defined(__gfx900__) // for GPU code
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#define CK_USE_AMD_V_MAC_F32
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#elif defined(__gfx906__) || defined(__gfx908__) || defined(__gfx90a__) || \
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defined(__gfx1030__) // for GPU code
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#define CK_USE_AMD_V_FMAC_F32
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#define CK_USE_AMD_V_DOT2_F32_F16
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#define CK_USE_AMD_V_DOT4_I32_I8
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#endif
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// MFMA instruction
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#ifndef __HIP_DEVICE_COMPILE__ // for host code
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#define CK_USE_AMD_MFMA
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#elif defined(__gfx908__) || defined(__gfx90a__) // for GPU code
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#define CK_USE_AMD_MFMA
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#endif
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#if defined(__gfx90a__)
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#define CK_USE_AMD_MFMA_BF16_1K_OP
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#endif
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// buffer load
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#define CK_USE_AMD_BUFFER_LOAD 1
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// buffer store
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#define CK_USE_AMD_BUFFER_STORE 1
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// buffer atomic add: integer
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#define CK_USE_AMD_BUFFER_ATOMIC_ADD_INTEGER 1
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// buffer atomic add: floating point
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#ifndef __HIP_DEVICE_COMPILE__ // for host code
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#define CK_USE_AMD_BUFFER_ATOMIC_ADD_FLOAT 1
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#elif defined(__gfx908__) || defined(__gfx90a__) // for GPU code
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#define CK_USE_AMD_BUFFER_ATOMIC_ADD_FLOAT 1
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#else // for GPU code
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#define CK_USE_AMD_BUFFER_ATOMIC_ADD_FLOAT 0
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#endif
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#if defined(__gfx90a__) // for GPU code
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#define CK_USE_AMD_BUFFER_ATOMIC_MAX_FLOAT64 1
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#else
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#define CK_USE_AMD_BUFFER_ATOMIC_MAX_FLOAT64 0
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#endif
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// inline asm
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#define CK_USE_AMD_INLINE_ASM 1
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// inner product (DLOP)
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#define CK_USE_AMD_INNER_PRODUCT_INLINE_ASM 1
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// block synchronization only s_wait lgkmcnt(0), not vmcnt(0)
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#define CK_EXPERIMENTAL_BLOCK_SYNC_LDS_WITHOUT_SYNC_VMEM 1
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// experimental feature: multi index implemented as array
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#define CK_EXPERIMENTAL_USE_DYNAMICALLY_INDEXED_MULTI_INDEX 0
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// experimental feature: static tensor descriptor
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#define CK_EXPERIMENTAL_STATIC_TENSOR_DESCRIPTOR 0
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// experimental feature: buffer load/store/atomic-add/ OOB trick
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// This (ifndef) is a hack to use customized behavior for buffer load rather than using default
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// setting. Don't use this hack unless absolutely necessary!
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// FIXME: make the behavior of buffer load a configurable (template) parameter for each usage
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#ifndef CK_EXPERIMENTAL_USE_BUFFER_LOAD_OOB_CHECK_OFFSET_TRICK
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#define CK_EXPERIMENTAL_USE_BUFFER_LOAD_OOB_CHECK_OFFSET_TRICK 0
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#endif
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#define CK_EXPERIMENTAL_USE_BUFFER_STORE_OOB_CHECK_OFFSET_TRICK 1
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#define CK_EXPERIMENTAL_USE_BUFFER_ATOMIC_ADD_OOB_CHECK_OFFSET_TRICK 1
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#define CK_EXPERIMENTAL_USE_BUFFER_ATOMIC_MAX_OOB_CHECK_OFFSET_TRICK 1
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// experimental feature: in-regsiter sub-dword transpose
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#define CK_EXPERIMENTAL_USE_IN_REGISTER_SUB_DWORD_TRANSPOSE 1
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// experimental feature: merge transformation use magic number division
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#define CK_EXPERIMENTAL_MERGE_USE_MAGIC_DIVISION 1
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// experimental feature: use __builtin_memcpy instead of pointer cast to access a vector from
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// pointer of scalar
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#define CK_EXPERIMENTAL_USE_MEMCPY_FOR_VECTOR_ACCESS 0
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// experimental feature: use __builtin_memcpy instead of union to do bit_cast
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#define CK_EXPERIMENTAL_USE_MEMCPY_FOR_BIT_CAST 1
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// experimental feature: optimize for inter-wave scheduling policy
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#define CK_EXPERIMENTAL_INTER_WAVE_SCHEDULING 0
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#define CK_EXPERIMENTAL_INTER_WAVE_SCHEDULING_MAC_CLUSTERS 1
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// hack: have underlying assumption that need to be satsified, otherwise it's a bug
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// hack for forcing register to keep idx_diff_low_const in SGPR. idx_diff_low_const must be
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// thread-invariant, otherwise it's a bug
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// TODO: separate index calculation into "compile-time", "global", "block", "wave", "thread"
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#define CK_HACK_MERGE_CALCULATE_IDX_DIFF_LOW_CONST_USE_AMD_GCN_READ_FIRST_LANE 0
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// workaround: compiler crash when compiling recursive lambda
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#define CK_WORKAROUND_SWDEV_275126 1
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// workaround: compiler crash when using buffer load/store for i8
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#define CK_WORKAROUND_SWDEV_XXXXXX_INT8_BUFFER_LOAD_STORE_ISSUE 1
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// workaround: compiler gnerating inefficient ds_write instructions
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#define CK_WORKAROUND_SWDEV_XXXXXX_INT8_DS_WRITE_ISSUE 1
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// (gfx908 only) workaround: compiler crash in fused kernels on mainline #9110; #10738 seems ok
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// error message was "fatal error: error in backend: Error while trying to spill VGPR0 from class
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// VGPR_32: Cannot scavenge register without an emergency spill slot!"
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// this fall back to less ideal way of handle NPadding in fused attention kernel
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#ifdef __gfx908__
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#define CK_WORKAROUND_SWDEV_XXXXXX_ATTN_KERNEL_CLANG_CANNOT_SCAVENGE_REGISTER 1
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#else
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// for __gfx90a__, ...
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#define CK_WORKAROUND_SWDEV_XXXXXX_ATTN_KERNEL_CLANG_CANNOT_SCAVENGE_REGISTER 0
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#endif // __gfx908__
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// workaround: verifaction failure, due to compiler regression, for conv bwd-data fp16 using some
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// tuning parameter
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#define CK_WORKAROUND_SWDEV_325164 0
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// workaround: disable broken fused attention kernel instance that does not pass validation
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// issue found on mi100/#10738 combo when irregular KPerBlock attention kernel has acc0 scaling
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// enabled
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#define CK_WORKAROUND_DISABLE_BROKEN_ATTN_KERNEL_INSTANCE 1
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namespace ck {
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enum struct InMemoryDataOperationEnum
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{
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Set,
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AtomicAdd,
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AtomicMax,
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Add
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};
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// FIXME: use regular Sequence and remove this
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template <InMemoryDataOperationEnum... Is>
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struct InMemoryDataOperationEnumSequence
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{
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static constexpr int mSize = sizeof...(Is);
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__host__ __device__ static constexpr InMemoryDataOperationEnum At(int I)
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{
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// the last dummy element is to prevent compiler complain about empty array, when mSize = 0
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const InMemoryDataOperationEnum mData[mSize + 1] = {Is..., InMemoryDataOperationEnum::Set};
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return mData[I];
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}
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};
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// index type
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using index_t = int32_t;
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using long_index_t = int64_t;
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} // namespace ck
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