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ed5010d65b
Standardize format of AMD copyright notice. AMD-Internal: [CPUPL-3519] Change-Id: I98530e58138765e5cd5bc0c97500506801eb0bf0
119 lines
4.6 KiB
C
119 lines
4.6 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018 - 2023, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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void* bli_thrcomm_bcast
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(
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dim_t id,
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void* to_send,
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thrcomm_t* comm
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)
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{
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if ( comm == NULL || comm->n_threads == 1 ) return to_send;
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if ( id == 0 ) comm->sent_object = to_send;
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bli_thrcomm_barrier( id, comm );
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void* object = comm->sent_object;
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bli_thrcomm_barrier( id, comm );
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return object;
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}
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// Use __sync_* builtins (assumed available) if __atomic_* ones are not present.
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#ifndef __ATOMIC_RELAXED
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#define __ATOMIC_RELAXED
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#define __ATOMIC_ACQUIRE
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#define __ATOMIC_RELEASE
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#define __ATOMIC_ACQ_REL
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#define __atomic_load_n(ptr, constraint) \
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__sync_fetch_and_add(ptr, 0)
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#define __atomic_add_fetch(ptr, value, constraint) \
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__sync_add_and_fetch(ptr, value)
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#define __atomic_fetch_add(ptr, value, constraint) \
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__sync_fetch_and_add(ptr, value)
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#define __atomic_fetch_xor(ptr, value, constraint) \
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__sync_fetch_and_xor(ptr, value)
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#endif
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void bli_thrcomm_barrier_atomic( dim_t t_id, thrcomm_t* comm )
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{
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// Return early if the comm is NULL or if there is only one
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// thread participating.
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if ( comm == NULL || comm->n_threads == 1 ) return;
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// Read the "sense" variable. This variable is akin to a unique ID for
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// the current barrier. The first n-1 threads will spin on this variable
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// until it changes. The sense variable gets incremented by the last
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// thread to enter the barrier, just before it exits. But it turns out
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// that you don't need many unique IDs before you can wrap around. In
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// fact, if everything else is working, a binary variable is sufficient,
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// which is what we do here (i.e., 0 is incremented to 1, which is then
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// decremented back to 0, and so forth).
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gint_t orig_sense = __atomic_load_n( &comm->barrier_sense, __ATOMIC_RELAXED );
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// Register ourselves (the current thread) as having arrived by
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// incrementing the barrier_threads_arrived variable. We must perform
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// this increment (and a subsequent read) atomically.
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dim_t my_threads_arrived =
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__atomic_add_fetch( &comm->barrier_threads_arrived, 1, __ATOMIC_ACQ_REL );
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// If the current thread was the last thread to have arrived, then
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// it will take actions that effectively ends and resets the barrier.
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if ( my_threads_arrived == comm->n_threads )
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{
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// Reset the variable tracking the number of threads that have arrived
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// to zero (which returns the barrier to the "empty" state. Then
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// atomically toggle the barrier sense variable. This will signal to
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// the other threads (which are spinning in the branch elow) that it
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// is now safe to exit the barrier.
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comm->barrier_threads_arrived = 0;
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__atomic_fetch_xor( &comm->barrier_sense, 1, __ATOMIC_RELEASE );
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}
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else
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{
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// If the current thread is NOT the last thread to have arrived, then
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// it spins on the sense variable until that sense variable changes at
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// which time these threads will exit the barrier.
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while ( __atomic_load_n( &comm->barrier_sense, __ATOMIC_ACQUIRE ) == orig_sense )
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; // Empty loop body.
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}
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}
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