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ed5010d65b
Standardize format of AMD copyright notice. AMD-Internal: [CPUPL-3519] Change-Id: I98530e58138765e5cd5bc0c97500506801eb0bf0
216 lines
5.1 KiB
C
216 lines
5.1 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018 - 2023, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BLIS_CONFIG_H
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#define BLIS_CONFIG_H
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// Enabled configuration "family" (config_name)
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@config_name_define@
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// Enabled sub-configurations (config_list)
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@config_list_defines@
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// Enabled kernel sets (kernel_list)
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@kernel_list_defines@
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//This macro is enabled only for ZEN family configurations.
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//This enables us to use different cache-blocking sizes for TRSM instead of common level-3 cache-block sizes.
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#if @enable_aocl_zen@
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#define AOCL_BLIS_ZEN
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#endif
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#if @enable_aocl_dynamic@
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#define AOCL_DYNAMIC
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#endif
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#if @enable_system@
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#define BLIS_ENABLE_SYSTEM
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#else
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#define BLIS_DISABLE_SYSTEM
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#endif
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#if @enable_openmp@
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#define BLIS_ENABLE_OPENMP
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#endif
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#if @enable_pthreads@
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#define BLIS_ENABLE_PTHREADS
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#endif
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#if @enable_jrir_slab@
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#define BLIS_ENABLE_JRIR_SLAB
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#endif
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#if @enable_jrir_rr@
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#define BLIS_ENABLE_JRIR_RR
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#endif
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#if @enable_pba_pools@
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#define BLIS_ENABLE_PBA_POOLS
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#else
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#define BLIS_DISABLE_PBA_POOLS
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#endif
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#if @enable_sba_pools@
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#define BLIS_ENABLE_SBA_POOLS
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#else
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#define BLIS_DISABLE_SBA_POOLS
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#endif
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#if @enable_mem_tracing@
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#define BLIS_ENABLE_MEM_TRACING
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#else
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#define BLIS_DISABLE_MEM_TRACING
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#endif
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#if @int_type_size@ == 64
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#define BLIS_INT_TYPE_SIZE 64
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#elif @int_type_size@ == 32
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#define BLIS_INT_TYPE_SIZE 32
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#else
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// determine automatically
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#endif
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#if @blas_int_type_size@ == 64
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#define BLIS_BLAS_INT_TYPE_SIZE 64
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#elif @blas_int_type_size@ == 32
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#define BLIS_BLAS_INT_TYPE_SIZE 32
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#else
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// determine automatically
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#endif
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#ifndef BLIS_ENABLE_BLAS
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#ifndef BLIS_DISABLE_BLAS
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#if @enable_blas@
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#define BLIS_ENABLE_BLAS
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#else
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#define BLIS_DISABLE_BLAS
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#endif
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#endif
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#endif
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#ifndef BLIS_ENABLE_CBLAS
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#ifndef BLIS_DISABLE_CBLAS
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#if @enable_cblas@
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#define BLIS_ENABLE_CBLAS
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#else
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#define BLIS_DISABLE_CBLAS
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#endif
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#endif
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#endif
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// If the CBLAS compatibility layer was enabled while the BLAS layer
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// was not enabled, we must enable the BLAS layer here. Also undefine
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// BLIS_DISABLE_BLAS to ensure consistency.
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#ifdef BLIS_ENABLE_CBLAS
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#ifndef BLIS_ENABLE_BLAS
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#define BLIS_ENABLE_BLAS
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#endif
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#undef BLIS_DISABLE_BLAS
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#endif // BLIS_ENABLE_CBLAS
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#ifndef BLIS_ENABLE_MIXED_DT
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#ifndef BLIS_DISABLE_MIXED_DT
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#if @enable_mixed_dt@
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#define BLIS_ENABLE_MIXED_DT
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#else
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#define BLIS_DISABLE_MIXED_DT
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#endif
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#endif
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#endif
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#ifndef BLIS_ENABLE_MIXED_DT_EXTRA_MEM
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#ifndef BLIS_DISABLE_MIXED_DT_EXTRA_MEM
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#if @enable_mixed_dt_extra_mem@
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#define BLIS_ENABLE_MIXED_DT_EXTRA_MEM
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#else
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#define BLIS_DISABLE_MIXED_DT_EXTRA_MEM
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#endif
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#endif
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#endif
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#if @enable_sup_handling@
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#define BLIS_ENABLE_SUP_HANDLING
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#else
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#define BLIS_DISABLE_SUP_HANDLING
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#endif
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#if @enable_memkind@
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#define BLIS_ENABLE_MEMKIND
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#else
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#define BLIS_DISABLE_MEMKIND
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#endif
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#if @enable_trsm_preinversion@
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#define BLIS_ENABLE_TRSM_PREINVERSION
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#else
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#define BLIS_DISABLE_TRSM_PREINVERSION
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#endif
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#if @enable_pragma_omp_simd@
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#define BLIS_ENABLE_PRAGMA_OMP_SIMD
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#else
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#define BLIS_DISABLE_PRAGMA_OMP_SIMD
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#endif
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#if @enable_sandbox@
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#define BLIS_ENABLE_SANDBOX
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#else
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#define BLIS_DISABLE_SANDBOX
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#endif
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#if @enable_shared@
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#define BLIS_ENABLE_SHARED
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#else
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#define BLIS_DISABLE_SHARED
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#endif
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#if @complex_return_intel@
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#define BLIS_ENABLE_COMPLEX_RETURN_INTEL
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#else
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#define BLIS_DISABLE_COMPLEX_RETURN_INTEL
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#endif
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#if @disable_blis_arch_type@
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#define DISABLE_BLIS_ARCH_TYPE
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#define DISABLE_BLIS_MODEL_TYPE
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#endif
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#define __blis_arch_type_name "@rename_blis_arch_type@"
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#define __blis_model_type_name "@rename_blis_model_type@"
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#endif
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