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- They didn't make much improvements. - Can't register row-preferral and column-preferral ukrs at the same time. Will break 1m.
145 lines
5.5 KiB
C
145 lines
5.5 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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void bli_cntx_init_firestorm( cntx_t* cntx )
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{
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blksz_t blkszs[ BLIS_NUM_BLKSZS ];
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blksz_t thresh[ BLIS_NUM_THRESH ];
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// Set default kernel blocksizes and functions.
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bli_cntx_init_firestorm_ref( cntx );
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// -------------------------------------------------------------------------
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// Update the context with optimized native gemm micro-kernels and
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// their storage preferences.
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bli_cntx_set_l3_nat_ukrs
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(
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2,
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BLIS_GEMM_UKR, BLIS_FLOAT, bli_sgemm_armv8a_asm_8x12, FALSE,
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BLIS_GEMM_UKR, BLIS_DOUBLE, bli_dgemm_armv8a_asm_6x8, FALSE,
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cntx
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);
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// Update the context with optimized packm kernels.
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bli_cntx_set_packm_kers
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(
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4,
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BLIS_PACKM_8XK_KER, BLIS_FLOAT, bli_spackm_armv8a_int_8xk,
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BLIS_PACKM_12XK_KER, BLIS_FLOAT, bli_spackm_armv8a_int_12xk,
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BLIS_PACKM_6XK_KER, BLIS_DOUBLE, bli_dpackm_armv8a_int_6xk,
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BLIS_PACKM_8XK_KER, BLIS_DOUBLE, bli_dpackm_armv8a_int_8xk,
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cntx
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);
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// Initialize level-3 blocksize objects with architecture-specific values.
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// s d c z
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bli_blksz_init_easy( &blkszs[ BLIS_MR ], 8, 6, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], 12, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], 120, 252, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], 640, 3072, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], 3072, 8192, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes (and multiples) for native execution.
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bli_cntx_set_blkszs
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(
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BLIS_NAT, 5,
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BLIS_NC, &blkszs[ BLIS_NC ], BLIS_NR,
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BLIS_KC, &blkszs[ BLIS_KC ], BLIS_KR,
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BLIS_MC, &blkszs[ BLIS_MC ], BLIS_MR,
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BLIS_NR, &blkszs[ BLIS_NR ], BLIS_NR,
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BLIS_MR, &blkszs[ BLIS_MR ], BLIS_MR,
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cntx
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);
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// -------------------------------------------------------------------------
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// Initialize sup thresholds with architecture-appropriate values.
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// s d c z
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bli_blksz_init_easy( &thresh[ BLIS_MT ], -1, 99, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_NT ], -1, 99, -1, -1 );
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bli_blksz_init_easy( &thresh[ BLIS_KT ], -1, 99, -1, -1 );
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// Initialize the context with the sup thresholds.
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bli_cntx_set_l3_sup_thresh
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(
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3,
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BLIS_MT, &thresh[ BLIS_MT ],
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BLIS_NT, &thresh[ BLIS_NT ],
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BLIS_KT, &thresh[ BLIS_KT ],
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cntx
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);
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// Update the context with optimized small/unpacked gemm kernels.
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bli_cntx_set_l3_sup_kers
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(
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8,
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BLIS_RRR, BLIS_DOUBLE, bli_dgemmsup_rv_armv8a_asm_6x8m, TRUE,
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BLIS_RRC, BLIS_DOUBLE, bli_dgemmsup_rd_armv8a_asm_6x8m, TRUE,
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BLIS_RCR, BLIS_DOUBLE, bli_dgemmsup_rv_armv8a_asm_6x8m, TRUE,
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BLIS_RCC, BLIS_DOUBLE, bli_dgemmsup_rv_armv8a_asm_6x8n, TRUE,
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BLIS_CRR, BLIS_DOUBLE, bli_dgemmsup_rv_armv8a_asm_6x8m, TRUE,
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BLIS_CRC, BLIS_DOUBLE, bli_dgemmsup_rd_armv8a_asm_6x8n, TRUE,
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BLIS_CCR, BLIS_DOUBLE, bli_dgemmsup_rv_armv8a_asm_6x8n, TRUE,
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BLIS_CCC, BLIS_DOUBLE, bli_dgemmsup_rv_armv8a_asm_6x8n, TRUE,
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cntx
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);
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// Initialize level-3 sup blocksize objects with architecture-specific
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// values.
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// s d c z
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bli_blksz_init_easy( &blkszs[ BLIS_MR ], -1, 6, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NR ], -1, 8, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_MC ], -1, 240, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_KC ], -1, 1024, -1, -1 );
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bli_blksz_init_easy( &blkszs[ BLIS_NC ], -1, 3072, -1, -1 );
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// Update the context with the current architecture's register and cache
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// blocksizes for small/unpacked level-3 problems.
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bli_cntx_set_l3_sup_blkszs
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(
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5,
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BLIS_NC, &blkszs[ BLIS_NC ],
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BLIS_KC, &blkszs[ BLIS_KC ],
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BLIS_MC, &blkszs[ BLIS_MC ],
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BLIS_NR, &blkszs[ BLIS_NR ],
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BLIS_MR, &blkszs[ BLIS_MR ],
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cntx
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);
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}
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