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0b19029342ffc530fa22ef20398a26221cb8f6ec
blis/frame
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praveeng 825363bd2a Merge code from master to amd-staging as on 2017_03_08 by praveeng
Change-Id: I80740081b2cb54c9b77a3e78b9fe540e170be23d
2017-03-08 15:43:42 +05:30
..
0
Reclassified amaxv operation as a level-1v kernel.
2016-10-04 14:24:59 -05:00
1
Checked in the SAMAX optimizations
2016-10-13 10:07:51 +05:30
1d
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
1f
Miscellaneous cleanups, fixes to recent commits.
2016-04-27 15:21:10 -05:00
1m
Merge branch 'master' into knl
2016-10-25 13:51:07 -05:00
2
Redesigned control tree infrastructure.
2016-08-26 19:04:45 -05:00
3
Added logic for packing matrix A and prefetching matrix C in Unpacked SGEMM code
2017-02-08 11:24:10 +05:30
base
Adjusted stride selection of ct in macrokernels.
2016-11-16 14:13:08 -06:00
compat
Added missing "level-0" BLAS [sd]cabs1_().
2017-02-09 11:54:59 -06:00
include
Switched to simpler trsm_r implementation.
2016-11-23 17:59:06 -06:00
ind
Consolidated 3m1/4m1 gemmtrsm, trsm ukernel code.
2016-11-02 17:45:18 -05:00
thread
Add automatic loop thread assignment.
2016-11-04 15:48:02 -05:00
util
removed a redundant copy operation in DNRM2
2016-11-22 12:15:33 +05:30
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