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0ce45e31479bc225f4d6d0cb556785b20c16dd25
blis/kernels
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S, Hari Govind 0ce45e3147 Changing ZGEMM SUP threshold logic for zen5 to fix performance regression (#233) 
- Revert the logical operator from OR (||) to AND (&&) in the DCOMPLEX
  (ZGEMM) SUP threshold condition for k <= 128. The previous change to
  OR logic was causing performance regressions for certain input sizes
  by incorrectly routing cases to the SUP path when the native path
  would be more optimal.
2025-10-17 11:25:33 +05:30
..
armsve
Merge commit 'cfa3db3f' into amd-main
2024-07-08 06:09:11 -04:00
armv7a
Add explicit handling for beta == 0 in armsve sd and armv7a d gemm ukrs.
2021-09-29 16:43:38 -05:00
armv8a
Armv8 Trash New Bulk Kernels
2021-10-08 02:35:58 +09:00
bgq
Replaced use of bool_t type with C99 bool.
2020-08-03 11:27:13 +05:30
bulldozer
Code cleanup: Copyright notices
2024-08-05 15:35:08 -04:00
generic
Added a dummy file to kernels/generic.
2017-11-21 12:34:20 -06:00
haswell
GCC 15 SUP kernel workaround (2)
2025-09-04 17:14:06 +01:00
knc
Remove UT-Austin from copyright headers' clause 3.
2018-12-04 14:31:06 -06:00
knl
Code cleanup: Copyright notices
2024-08-05 15:35:08 -04:00
old
Remove UT-Austin from copyright headers' clause 3.
2018-12-04 14:31:06 -06:00
penryn
Optionally disable trsm diagonal pre-inversion.
2020-12-04 16:08:15 -06:00
piledriver
Code cleanup: Miscellaneous fixes
2024-08-06 06:56:01 -04:00
power7
Remove UT-Austin from copyright headers' clause 3.
2018-12-04 14:31:06 -06:00
power9
Merge commit 'e366665c' into amd-main
2023-10-18 09:09:54 -04:00
power10
Code cleanup: No newline at end of file
2023-04-21 10:02:48 -04:00
sandybridge
BLIS: Missing clobbers (batch 7)
2023-11-22 17:51:46 -05:00
skx
Code cleanup: Copyright notices
2024-08-05 15:35:08 -04:00
zen
Disabled no post-ops path in lpgemm f32 kernels for few gcc versions
2025-09-22 15:52:21 +05:30
zen2
Code cleanup: AMD copyright notice
2023-11-23 08:54:31 -05:00
zen3
Added support for zen3 configuration
2020-07-22 18:24:26 +05:30
zen4
Improved fringe case handling for AVXPV kernel (#228)
2025-10-10 14:25:35 +05:30
zen5
Changing ZGEMM SUP threshold logic for zen5 to fix performance regression (#233)
2025-10-17 11:25:33 +05:30
CMakeLists.txt
Renaming CMAKE_SOURCE_DIR to PROJECT_SOURCE_DIR so that BLIS can be built properly via FetchContent() (#65)
2025-08-07 15:51:59 +01:00