Harsh Dave f17d043e1c Implemented optimal dotxv kernel ...

Details:
- Intrinsic implementation of zdotxv, cdotxv kernel
- Unrolling in multiple of 8, remaining corner
  cases are handled serially for zdotxv kernel
- Unrolling in multiple of 16, remainig corner
  cases are handled serially for cdotxv kernel
- Added declaration in zen contexts

AMD-Internal: [CPUPL-2050]
Change-Id: Id58b0dbfdb7a782eb50eecc7142f051b630d9211

2022-05-17 18:10:39 +05:30

..

bli_amaxv_zen_int.c

Level1 samaxv: AVX512 implementation

2021-09-27 16:10:08 +05:30

bli_axpbyv_zen_int10.c

Optimized AXPBYV Kernel using AVX2 Intrinsics

2022-01-05 04:19:11 -05:00

bli_axpbyv_zen_int.c

Optimized AXPBYV Kernel using AVX2 Intrinsics

2022-01-05 04:19:11 -05:00

bli_axpyv_zen_int10.c

Improved AXPYV Kernel performance

2021-12-20 13:21:20 +05:30

bli_axpyv_zen_int.c

This check in has changes w.r.t Copyright information, which is changed to (start year) - 2019

2019-05-27 16:24:43 +05:30

bli_copyv_zen_int.c

Squash-merge 'pr' into 'squash'. (#457)

2020-11-14 09:39:48 -06:00

bli_dotv_zen_int10.c

BLIS:merge:

2021-04-27 11:09:48 +05:30

bli_dotv_zen_int.c

Rebased amd-staging-milan-3.0 branch on master

2020-08-06 10:09:29 +05:30

bli_dotxv_zen_int.c

Implemented optimal dotxv kernel

2022-05-17 18:10:39 +05:30

bli_norm2_zen_int.c

dnrm2 optimization with dot method

2021-11-12 08:58:53 +05:30

bli_scalv_zen_int10.c

Removed Arch specific code from BLIS framework.

2022-01-18 11:51:08 +05:30

bli_scalv_zen_int.c

This check in has changes w.r.t Copyright information, which is changed to (start year) - 2019

2019-05-27 16:24:43 +05:30

bli_setv_zen_int.c

Squash-merge 'pr' into 'squash'. (#457)

2020-11-14 09:39:48 -06:00

bli_swapv_zen_int8.c

BLIS:merge:

2021-04-27 11:09:48 +05:30

CMakeLists.txt

Optimized AXPBYV Kernel using AVX2 Intrinsics

2022-01-05 04:19:11 -05:00