Eleni Vlachopoulou ad7a812db2 Remove quick return for zero increments. ...

Details:
- To be BLAS compliant, if increment is zero then iterate through the first element n times.
- For n<=0, the correct result (0) is returned so we remove this extra check. This is checked on BLIS-typed interface level.

AMD-Internal: [SWLCSG-1900]
Change-Id: I098bb9560a790050018bc8d8c63b06bfbcc1aebd

2023-03-23 23:35:03 -04:00

..

bli_amaxv_zen_int.c

Modified Double precision AMAXV kernel

2023-03-21 05:18:05 -04:00

bli_axpbyv_zen_int10.c

Optimized AXPBYV Kernel using AVX2 Intrinsics

2022-01-05 04:19:11 -05:00

bli_axpbyv_zen_int.c

Optimized AXPBYV Kernel using AVX2 Intrinsics

2022-01-05 04:19:11 -05:00

bli_axpyv_zen_int10.c

Improved performance of double complex AXPYV kernel

2023-03-02 00:35:42 -05:00

bli_axpyv_zen_int.c

This check in has changes w.r.t Copyright information, which is changed to (start year) - 2019

2019-05-27 16:24:43 +05:30

bli_copyv_zen_int.c

Vectorized COPYV for double complex

2023-02-16 09:32:10 -05:00

bli_dotv_zen_int10.c

BLIS:merge:

2021-04-27 11:09:48 +05:30

bli_dotv_zen_int.c

Rebased amd-staging-milan-3.0 branch on master

2020-08-06 10:09:29 +05:30

bli_dotxv_zen_int.c

Implemented optimal dotxv kernel

2022-05-17 18:10:39 +05:30

bli_norm2_zen_int.c

Remove quick return for zero increments.

2023-03-23 23:35:03 -04:00

bli_scal2v_zen_int.c

Added vector packing logic to ZGEMV variant 2

2023-03-22 03:19:18 -04:00

bli_scalv_zen_int10.c

AVX2 vectorized SCALV for double complex

2023-02-05 09:36:12 -05:00

bli_scalv_zen_int.c

This check in has changes w.r.t Copyright information, which is changed to (start year) - 2019

2019-05-27 16:24:43 +05:30

bli_setv_zen_int.c

Squash-merge 'pr' into 'squash'. (#457)

2020-11-14 09:39:48 -06:00

bli_swapv_zen_int8.c

BLIS:merge:

2021-04-27 11:09:48 +05:30

CMakeLists.txt

Vectorized SCAL2V for double complex

2023-02-28 06:59:23 -05:00