Harihara Sudhan S 18ae57305e ZAXPYF4 optimization ...

- Vectorized alpha scaling of X vector using SSE instructions. This
  can be done irrespective of incx.
- Added code to prefetch A matrix and Y vector to L1 cache
- Vectorized fringe case computation and non-unit stride computation
  with SSE instructions.
- Increased unroll in unit stride cases for better register
  utilization.

AMD-Internal: [CPUPL-2773]
Change-Id: I217e6ce9e3f5753ebe271c684abd9a2274fd2715

2023-02-04 12:34:50 -05:00

..

bli_axpy2v_zen_int.c

Removed Arch specific code from BLIS framework.

2022-05-17 20:35:40 +05:30

bli_axpyf_zen_int_4.c

ZAXPYF4 optimization

2023-02-04 12:34:50 -05:00

bli_axpyf_zen_int_5.c

Tuned aocl dynamic for specific range in dgemm

2022-05-17 18:10:39 +05:30

bli_axpyf_zen_int_6.c

Removed Arch specific code from BLIS framework.

2022-01-18 11:51:08 +05:30

bli_axpyf_zen_int_8.c

Improved DGEMV performance for column-major cases

2022-02-02 23:13:10 -05:00

bli_dotxaxpyf_zen_int_8.c

Optimized S/DCOMPLEX DOTXAXPYF using AVX2 Intrinsics

2022-05-17 18:10:39 +05:30

bli_dotxf_zen_int_8.c

Implemented optimal S/DCOMPLEX dotxf kernel

2022-01-06 02:22:52 -05:00

CMakeLists.txt

Removed Arch specific code from BLIS framework.

2022-05-17 20:35:40 +05:30