Mangala V 503e912fc5 Merge "Modified blas interface of TRSM to call TRSV whenever m=1 or n=1." into amd-staging-milan-3.1

2021-02-11 00:21:45 -05:00

..

0

Removed export macros from all internal prototypes.

2020-08-03 11:47:18 +05:30

1

Added debug trace and log support for copy and ger routines

2020-11-02 22:56:58 -05:00

1d

Removed export macros from all internal prototypes.

2020-08-03 11:47:18 +05:30

1f

Removed export macros from all internal prototypes.

2020-08-03 11:47:18 +05:30

1m

Annotated additional symbols for export.

2020-08-03 11:47:18 +05:30

2

Modified blas interface of TRSM to call TRSV whenever m=1 or n=1.

2021-02-08 19:02:25 +05:30

3

Improve sup GEMM performance (CCC - row prefer kernel)

2020-12-10 19:16:44 +05:30

base

Handling zgemm real(+/-1) alpha and beta

2021-02-10 02:58:58 -05:00

compat

Modified blas interface of TRSM to call TRSV whenever m=1 or n=1.

2021-02-11 18:47:37 +05:30

include

Adpative zgemm

2021-02-03 12:43:57 +05:30

ind

Adpative zgemm

2021-02-03 12:43:57 +05:30

thread

Fixed missing changes

2020-08-13 00:29:37 +05:30

util

BLIS library porting on to Windows:

2020-08-06 10:09:29 +05:30

CMakeLists.txt

BLIS library porting on to Windows:

2020-06-16 18:29:00 +05:30