Mangala V 503e912fc5 Merge "Modified blas interface of TRSM to call TRSV whenever m=1 or n=1." into amd-staging-milan-3.1

2021-02-11 00:21:45 -05:00

..

1

Added debug log support for axpy, axpyb, amax, asum, hemv, her2

2020-11-03 20:44:12 +05:30

1f

Modified blas interface of TRSM to call TRSV whenever m=1 or n=1.

2021-02-11 18:47:37 +05:30

1m

BLIS library porting on to Windows:

2020-06-16 18:29:00 +05:30

2

Enabling framework optimizations for zen family architectures.

2020-10-07 13:10:50 +05:30

3

Handling zgemm real(+/-1) alpha and beta

2021-02-10 02:58:58 -05:00

bli_kernels_zen.h

Added 16x4 AXPYF kernel for zen2 config

2021-02-02 21:22:44 +05:30

CMakeLists.txt

Cmake script changes and blis.h changes for amd-staging-milan-3.0

2020-11-24 06:12:25 -05:00