c665eb9b88
Details:
- Changed all occurrances of
micro-kernel -> microkernel
macro-kernel -> macrokernel
micro-panel -> micropanel
in all markdown documents in 'docs' directory. This change is being
made since we've reached the point in adoption and acceptance of
BLIS's insights where words such as "microkernel" are no longer new,
and therefore now merit being unhyphenated.
- Updated "Implementation Notes" sections of KernelsHowTo.md, which
still contained references to nonexistent cpp macros such as
BLIS_DEFAULT_MR_? and BLIS_PACKDIM_MR_?.
- Added 'run-fast' and 'check-fast' targets to testsuite/Makefile.
- Minor updates to Testsuite.md, including suggesting use of
'make check' and 'make check-fast' when running from the local
testsuite directory.
- Added a comment to top-level Makefile explaining the purpose behind
the TESTSUITE_WRAPPER variable, which at first glance appears to serve
no purpose.
4.1 KiB
Introduction
This wiki is intended to track the support for various hardware types within the BLIS framework source distribution.
We apologize if this wiki falls out of date. For the latest support, we recommend peeking inside of the relevant sub-configuration (specifically, in the bli_cntx_init_<configname>.c file) and looking at which kernels are registered. You may also contact the blis-devel mailing list.
Level-3 microkernels
The following table lists architectures for which there exist optimized level-3 microkernels, which microkernels are optimized, the name of the author or maintainer, and the current status of the microkernels.
A few remarks / reminders:
- Optimizing only the gemm microkernel will result in optimal performance for all level-3 operations except
trsm(which will typically achieve 60 - 80% of attainable peak performance). - The trsm operation needs the gemmtrsm microkernel(s), in addition to the aforementioned gemm microkernel, in order reach optimal performance.
- Induced complex (1m) implementations are employed in all situations where the real domain gemm microkernel of the corresponding precision is available. Please see our ACM TOMS article on the 1m method for more info on this topic.
- Some microarchitectures use the same sub-configuration. This is not a typo. For example, Haswell and Broadwell systems as well as "desktop" (non-server) versions of Skylake, Kabylake, and Coffeelake all use the
haswellsub-configuration and the kernels registered therein. - Remember that you (usually) don't have to choose your sub-configuration manually! Instead, you can always request configure-time hardware detection via
./configure auto. This will defer to internal logic (based on CPUID for x86_64 systems) that will attempt to choose the appropriate sub-configuration automatically.
| Vendor/Microarchitecture | BLIS sub-configuration | gemm |
gemmtrsm |
|---|---|---|---|
| AMD Bulldozer (AVX/FMA4) | bulldozer |
sdcz |
|
| AMD Piledriver (AVX/FMA3) | piledriver |
sdcz |
|
| AMD Steamroller (AVX/FMA3) | steamroller |
sdcz |
|
| AMD Excavator (AVX/FMA3) | excavator |
sdcz |
|
| AMD Zen (AVX/FMA3) | zen |
sdcz |
sd |
| Intel Core2 (SSE3) | penryn |
sd |
d |
| Intel Sandy/Ivy Bridge (AVX/FMA3) | sandybridge |
sdcz |
|
| Intel Haswell, Broadwell (AVX/FMA3) | haswell |
sdcz |
sd |
| Intel Sky/Kaby/Coffeelake (AVX/FMA3) | haswell |
sdcz |
sd |
| Intel Knights Landing (AVX-512/FMA3) | knl |
sd |
|
| Intel SkylakeX (AVX-512/FMA3) | skx |
sd |
|
| ARMv7 Cortex-A9 (NEON) | cortex-a9 |
sd |
|
| ARMv7 Cortex-A15 (NEON) | cortex-a15 |
sd |
|
| ARMv8 Cortex-A53 (NEON) | cortex-a53 |
sd |
|
| ARMv8 Cortex-A57 (NEON) | cortex-a57 |
sd |
|
| IBM Blue Gene/Q (QPX int) | bgq |
d |
|
| IBM Power7 (QPX int) | power7 |
d |
|
| template (C99) | template |
sdcz |
sdcz |
Level-1f kernels
Not yet written. Please see the relevant sub-configuration (bli_cntx_init_<configname>.c) to determine which kernels are implemented/registered.
Level-1v kernels
Not yet written. Please see the relevant sub-configuration (bli_cntx_init_<configname>.c) to determine which kernels are implemented/registered.