Abhiram S 7787bc79b1 Level1 samaxv: AVX512 implementation ...

Details:
 1. Unrolled by a factor 5. This gave around 1GFLOPS gain
 2. Changed CMP to subs and remove nan. CMP uses a lot of
    compare, which is higher in latency and more number of
    instructions. Replacing with subs and remove nan
    reduced it to 3 instructions and lighter ones.
 3. Added remove nan function.
 4. Added AVX512 definition in skx context.
 5. Disabled code in AMAXV kernel depending on AVX512 flag
    exists or not

Change-Id: I191725a55bc33edf8d537156292cf997d6a5fe35

2021-09-27 16:10:08 +05:30

..

1

Level1 samaxv: AVX512 implementation

2021-09-27 16:10:08 +05:30

1f

AOCL-Windows: Update BLIS build system

2021-06-15 16:49:08 +05:30

1m

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

2

Enabling framework optimizations for zen family architectures.

2020-10-07 13:10:50 +05:30

3

Combined variants to reduce redundancy in dtrsm small

2021-08-26 15:04:14 +05:30

util

Added a new field in cntx to store l3 threshold function pointers

2021-08-16 00:10:01 -04:00

bli_kernels_zen.h

Level1 samaxv: AVX512 implementation

2021-09-27 16:10:08 +05:30

CMakeLists.txt

Added a new field in cntx to store l3 threshold function pointers

2021-08-16 00:10:01 -04:00