Aayush Kumar 6ad387c2aa Added DTRSM Small Path AVX512 based LUNN/LLTN Variant Kernels ...

- 8x8 kernels are used for DTRSM SMALL
- Matrix A(a10) is packed for GEMM operations.
- Packed martix A will be re-used in all the col-block
  along N-dimension.
- Diagonal elements of A matrix are packed(a11) for
  TRSM operations.
- Implemented fringe cases with below block sizes
   8x8, 8x4, 8x3, 8x2, 8x1
   4x8, 4x4, 4x3, 4x2, 4x1
   3x8, 3x4, 3x3, 3x2, 3x1
   2x8, 2x4, 2x3, 2x2, 2x1
   1x8, 1x4, 1x3, 1x2, 1x1

AMD-Internal: [CPUPL-2745]

Change-Id: I5bb57501f6d3783eb654e375d63901467dd14734

2023-04-13 01:44:31 -04:00

..

armsve

New kernel set for Arm SVE using assembly (#396)

2020-05-21 11:56:45 +05:30

armv7a

Squash-merge 'pr' into 'squash'. (#457)

2020-11-14 09:39:48 -06:00

armv8a

avoid loading twice in armv8a gemm kernel (#403)

2020-05-21 12:37:53 +05:30

bgq

Replaced use of bool_t type with C99 bool.

2020-08-03 11:27:13 +05:30

bulldozer

Remove UT-Austin from copyright headers' clause 3.

2018-12-04 14:31:06 -06:00

generic

Added a dummy file to kernels/generic.

2017-11-21 12:34:20 -06:00

haswell

Fixed ASAN memory issue due to modifying RBP register

2023-03-23 21:23:44 -04:00

knc

Remove UT-Austin from copyright headers' clause 3.

2018-12-04 14:31:06 -06:00

knl

Type saga continues; fixed sgemm ukernel signature.

2020-09-12 17:48:15 -05:00

old

Remove UT-Austin from copyright headers' clause 3.

2018-12-04 14:31:06 -06:00

penryn

Optionally disable trsm diagonal pre-inversion.

2020-12-04 16:08:15 -06:00

piledriver

BLIS library porting on to Windows:

2020-06-16 18:29:00 +05:30

power7

Remove UT-Austin from copyright headers' clause 3.

2018-12-04 14:31:06 -06:00

power9

Add POWER10 support to BLIS (#450)

2020-09-29 16:52:18 -05:00

power10

Fixed bug in power10 microkernel I/O. (#488)

2021-03-30 19:07:42 -05:00

sandybridge

Remove UT-Austin from copyright headers' clause 3.

2018-12-04 14:31:06 -06:00

skx

Bug Fix to replace vzeroall

2022-07-22 03:42:17 -04:00

zen

Added DTRSM Small Path AVX512 based LLNN/LUTN Variant Kernels

2023-04-07 08:50:28 +00:00

zen2

BLIS:merge:

2021-04-27 11:09:48 +05:30

zen3

Added support for zen3 configuration

2020-07-22 18:24:26 +05:30

zen4

Added DTRSM Small Path AVX512 based LUNN/LLTN Variant Kernels

2023-04-13 01:44:31 -04:00

CMakeLists.txt

Added support for AVX512 for Windows and AMAVX

2022-06-08 11:09:48 +05:30