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7038bbaa05
Details: - Implemented a configure-time option, --disable-trsm-preinversion, that optionally disables the pre-inversion of diagonal elements of the triangular matrix in the trsm operation and instead uses division instructions within the gemmtrsm microkernels. Pre-inversion is enabled by default. When it is disabled, performance may suffer slightly, but numerical robustness should improve for certain pathological cases involving denormal (subnormal) numbers that would otherwise result in overflow in the pre-inverted value. Thanks to Bhaskar Nallani for reporting this issue via #461. - Added preprocessor macro guards to bli_trsm_cntl.c as well as the gemmtrsm microkernels for 'haswell' and 'penryn' kernel sets pursuant to the aforementioned feature. - Added macros to frame/include/bli_x86_asm_macros.h related to division instructions.
552 lines
15 KiB
C
552 lines
15 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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#define BLIS_ASM_SYNTAX_ATT
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#include "bli_x86_asm_macros.h"
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#if 0
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void bli_sgemmtrsm_u_penryn_asm_8x4
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(
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dim_t k0,
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float* restrict alpha,
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float* restrict a12,
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float* restrict a11,
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float* restrict b21,
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float* restrict b11,
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float* restrict c11, inc_t rs_c0, inc_t cs_c0,
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auxinfo_t* restrict data,
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cntx_t* restrict cntx
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)
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{
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}
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#endif
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void bli_dgemmtrsm_u_penryn_asm_4x4
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(
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dim_t k0,
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double* restrict alpha,
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double* restrict a12,
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double* restrict a11,
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double* restrict b21,
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double* restrict b11,
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double* restrict c11, inc_t rs_c0, inc_t cs_c0,
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auxinfo_t* restrict data,
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cntx_t* restrict cntx
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)
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{
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void* b_next = bli_auxinfo_next_b( data );
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// Typecast local copies of integers in case dim_t and inc_t are a
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// different size than is expected by load instructions.
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uint64_t k_iter = k0 / 4;
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uint64_t k_left = k0 % 4;
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uint64_t rs_c = rs_c0;
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uint64_t cs_c = cs_c0;
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begin_asm()
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mov(var(a12), rax) // load address of a12.
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mov(var(b21), rbx) // load address of b21.
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//mov(var(b_next), r9) // load address of b_next.
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add(imm(8*16), rax) // increment pointers to allow byte
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add(imm(8*16), rbx) // offsets in the unrolled iterations.
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movaps(mem(rax, -8*16), xmm0) // initialize loop by pre-loading elements
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movaps(mem(rax, -7*16), xmm1) // of a and b.
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movaps(mem(rbx, -8*16), xmm2)
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xorpd(xmm3, xmm3)
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xorpd(xmm4, xmm4)
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xorpd(xmm5, xmm5)
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xorpd(xmm6, xmm6)
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xorpd(xmm8, xmm8)
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movaps(xmm8, xmm9)
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movaps(xmm8, xmm10)
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movaps(xmm8, xmm11)
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movaps(xmm8, xmm12)
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movaps(xmm8, xmm13)
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movaps(xmm8, xmm14)
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movaps(xmm8, xmm15)
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mov(var(k_iter), rsi) // i = k_iter;
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test(rsi, rsi) // check i via logical AND.
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je(.CONSIDERKLEFT) // if i == 0, jump to code that
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// contains the k_left loop.
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label(.LOOPKITER) // MAIN LOOP
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prefetch(0, mem(rax, 1264))
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addpd(xmm3, xmm11) // iteration 0
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movaps(mem(rbx, -7*16), xmm3)
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addpd(xmm4, xmm15)
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movaps(xmm2, xmm4)
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pshufd(imm(0x4e), xmm2, xmm7)
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mulpd(xmm0, xmm2)
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mulpd(xmm1, xmm4)
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addpd(xmm5, xmm10)
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addpd(xmm6, xmm14)
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movaps(xmm7, xmm6)
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mulpd(xmm0, xmm7)
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mulpd(xmm1, xmm6)
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addpd(xmm2, xmm9)
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movaps(mem(rbx, -6*16), xmm2)
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addpd(xmm4, xmm13)
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movaps(xmm3, xmm4)
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pshufd(imm(0x4e), xmm3, xmm5)
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mulpd(xmm0, xmm3)
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mulpd(xmm1, xmm4)
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addpd(xmm7, xmm8)
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addpd(xmm6, xmm12)
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movaps(xmm5, xmm6)
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mulpd(xmm0, xmm5)
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movaps(mem(rax, -6*16), xmm0)
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mulpd(xmm1, xmm6)
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movaps(mem(rax, -5*16), xmm1)
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addpd(xmm3, xmm11) // iteration 1
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movaps(mem(rbx, -5*16), xmm3)
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addpd(xmm4, xmm15)
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movaps(xmm2, xmm4)
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pshufd(imm(0x4e), xmm2, xmm7)
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mulpd(xmm0, xmm2)
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mulpd(xmm1, xmm4)
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addpd(xmm5, xmm10)
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addpd(xmm6, xmm14)
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movaps(xmm7, xmm6)
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mulpd(xmm0, xmm7)
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mulpd(xmm1, xmm6)
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addpd(xmm2, xmm9)
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movaps(mem(rbx, -4*16), xmm2)
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addpd(xmm4, xmm13)
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movaps(xmm3, xmm4)
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pshufd(imm(0x4e), xmm3, xmm5)
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mulpd(xmm0, xmm3)
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mulpd(xmm1, xmm4)
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addpd(xmm7, xmm8)
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addpd(xmm6, xmm12)
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movaps(xmm5, xmm6)
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mulpd(xmm0, xmm5)
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movaps(mem(rax, -4*16), xmm0)
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mulpd(xmm1, xmm6)
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movaps(mem(rax, -3*16), xmm1)
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prefetch(0, mem(rax, 1328))
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addpd(xmm3, xmm11) // iteration 2
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movaps(mem(rbx, -3*16), xmm3)
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addpd(xmm4, xmm15)
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movaps(xmm2, xmm4)
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pshufd(imm(0x4e), xmm2, xmm7)
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mulpd(xmm0, xmm2)
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mulpd(xmm1, xmm4)
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addpd(xmm5, xmm10)
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addpd(xmm6, xmm14)
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movaps(xmm7, xmm6)
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mulpd(xmm0, xmm7)
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mulpd(xmm1, xmm6)
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addpd(xmm2, xmm9)
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movaps(mem(rbx, -2*16), xmm2)
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addpd(xmm4, xmm13)
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movaps(xmm3, xmm4)
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pshufd(imm(0x4e), xmm3, xmm5)
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mulpd(xmm0, xmm3)
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mulpd(xmm1, xmm4)
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addpd(xmm7, xmm8)
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addpd(xmm6, xmm12)
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movaps(xmm5, xmm6)
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mulpd(xmm0, xmm5)
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movaps(mem(rax, -2*16), xmm0)
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mulpd(xmm1, xmm6)
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movaps(mem(rax, -1*16), xmm1)
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addpd(xmm3, xmm11) // iteration 3
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movaps(mem(rbx, -1*16), xmm3)
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addpd(xmm4, xmm15)
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movaps(xmm2, xmm4)
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pshufd(imm(0x4e), xmm2, xmm7)
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mulpd(xmm0, xmm2)
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mulpd(xmm1, xmm4)
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addpd(xmm5, xmm10)
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addpd(xmm6, xmm14)
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movaps(xmm7, xmm6)
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mulpd(xmm0, xmm7)
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mulpd(xmm1, xmm6)
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add(imm(4*4*8), rax) // a += 4*4 (unroll x mr)
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addpd(xmm2, xmm9)
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movaps(mem(rbx, 0*16), xmm2)
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addpd(xmm4, xmm13)
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movaps(xmm3, xmm4)
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pshufd(imm(0x4e), xmm3, xmm5)
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mulpd(xmm0, xmm3)
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mulpd(xmm1, xmm4)
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add(imm(4*4*8), rbx) // b += 4*4 (unroll x nr)
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addpd(xmm7, xmm8)
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addpd(xmm6, xmm12)
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movaps(xmm5, xmm6)
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mulpd(xmm0, xmm5)
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movaps(mem(rax, -8*16), xmm0)
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mulpd(xmm1, xmm6)
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movaps(mem(rax, -7*16), xmm1)
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dec(rsi) // i -= 1;
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jne(.LOOPKITER) // iterate again if i != 0.
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label(.CONSIDERKLEFT)
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mov(var(k_left), rsi) // i = k_left;
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test(rsi, rsi) // check i via logical AND.
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je(.POSTACCUM) // if i == 0, we're done; jump to end.
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// else, we prepare to enter k_left loop.
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label(.LOOPKLEFT) // EDGE LOOP
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addpd(xmm3, xmm11) // iteration 0
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movaps(mem(rbx, -7*16), xmm3)
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addpd(xmm4, xmm15)
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movaps(xmm2, xmm4)
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pshufd(imm(0x4e), xmm2, xmm7)
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mulpd(xmm0, xmm2)
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mulpd(xmm1, xmm4)
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addpd(xmm5, xmm10)
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addpd(xmm6, xmm14)
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movaps(xmm7, xmm6)
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mulpd(xmm0, xmm7)
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mulpd(xmm1, xmm6)
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addpd(xmm2, xmm9)
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movaps(mem(rbx, -6*16), xmm2)
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addpd(xmm4, xmm13)
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movaps(xmm3, xmm4)
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pshufd(imm(0x4e), xmm3, xmm5)
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mulpd(xmm0, xmm3)
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mulpd(xmm1, xmm4)
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addpd(xmm7, xmm8)
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addpd(xmm6, xmm12)
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movaps(xmm5, xmm6)
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mulpd(xmm0, xmm5)
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movaps(mem(rax, -6*16), xmm0)
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mulpd(xmm1, xmm6)
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movaps(mem(rax, -5*16), xmm1)
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add(imm(4*1*8), rax) // a += 4 (1 x mr)
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add(imm(4*1*8), rbx) // b += 4 (1 x nr)
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dec(rsi) // i -= 1;
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jne(.LOOPKLEFT) // iterate again if i != 0.
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label(.POSTACCUM)
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addpd(xmm3, xmm11)
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addpd(xmm4, xmm15)
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addpd(xmm5, xmm10)
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addpd(xmm6, xmm14)
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mov(var(b11), rbx) // load address of b11.
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// xmm8: xmm9: xmm10: xmm11:
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// ( ab01 ( ab00 ( ab03 ( ab02
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// ab10 ) ab11 ) ab12 ) ab13 )
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//
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// xmm12: xmm13: xmm14: xmm15:
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// ( ab21 ( ab20 ( ab23 ( ab22
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// ab30 ) ab31 ) ab32 ) ab33 )
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movaps(xmm9, xmm0)
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movaps(xmm8, xmm1)
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unpcklpd(xmm8, xmm0)
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unpckhpd(xmm9, xmm1)
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movaps(xmm11, xmm4)
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movaps(xmm10, xmm5)
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unpcklpd(xmm10, xmm4)
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unpckhpd(xmm11, xmm5)
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movaps(xmm13, xmm2)
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movaps(xmm12, xmm3)
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unpcklpd(xmm12, xmm2)
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unpckhpd(xmm13, xmm3)
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movaps(xmm15, xmm6)
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movaps(xmm14, xmm7)
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unpcklpd(xmm14, xmm6)
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unpckhpd(xmm15, xmm7)
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// xmm0: ( ab00 ab01 ) xmm4: ( ab02 ab03 )
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// xmm1: ( ab10 ab11 ) xmm5: ( ab12 ab13 )
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// xmm2: ( ab20 ab21 ) xmm6: ( ab22 ab23 )
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// xmm3: ( ab30 ab31 ) xmm7: ( ab32 ab33 )
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mov(var(alpha), rax) // load address of alpha
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movddup(mem(rax), xmm15) // load alpha and duplicate
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movaps(mem(rbx, 0*16), xmm8)
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movaps(mem(rbx, 1*16), xmm12)
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mulpd(xmm15, xmm8) // xmm8 = alpha * ( beta00 beta01 )
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mulpd(xmm15, xmm12) // xmm12 = alpha * ( beta02 beta03 )
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movaps(mem(rbx, 2*16), xmm9)
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movaps(mem(rbx, 3*16), xmm13)
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mulpd(xmm15, xmm9) // xmm9 = alpha * ( beta10 beta11 )
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mulpd(xmm15, xmm13) // xmm13 = alpha * ( beta12 beta13 )
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movaps(mem(rbx, 4*16), xmm10)
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movaps(mem(rbx, 5*16), xmm14)
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mulpd(xmm15, xmm10) // xmm10 = alpha * ( beta20 beta21 )
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mulpd(xmm15, xmm14) // xmm14 = alpha * ( beta22 beta23 )
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movaps(mem(rbx, 6*16), xmm11)
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mulpd(xmm15, xmm11) // xmm11 = alpha * ( beta30 beta31 )
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mulpd(mem(rbx, 7*16), xmm15) // xmm15 = alpha * ( beta32 beta33 )
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// (Now scaled by alpha:)
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// xmm8: ( beta00 beta01 ) xmm12: ( beta02 beta03 )
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// xmm9: ( beta10 beta11 ) xmm13: ( beta12 beta13 )
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// xmm10: ( beta20 beta21 ) xmm14: ( beta22 beta23 )
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// xmm11: ( beta30 beta31 ) xmm15: ( beta32 beta33 )
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subpd(xmm0, xmm8) // xmm8 -= xmm0
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subpd(xmm1, xmm9) // xmm9 -= xmm1
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subpd(xmm2, xmm10) // xmm10 -= xmm2
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subpd(xmm3, xmm11) // xmm11 -= xmm3
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subpd(xmm4, xmm12) // xmm12 -= xmm4
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subpd(xmm5, xmm13) // xmm13 -= xmm5
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subpd(xmm6, xmm14) // xmm14 -= xmm6
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subpd(xmm7, xmm15) // xmm15 -= xmm7
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label(.TRSM)
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mov(var(a11), rax) // load address of a11
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mov(var(c11), rcx) // load address of c11
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mov(var(rs_c), rsi) // load rs_c
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mov(var(cs_c), rdi) // load cs_c
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sal(imm(3), rsi) // rs_c *= sizeof( double )
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sal(imm(3), rdi) // cs_c *= sizeof( double )
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add(rsi, rcx) // c11 += (4-1)*rs_c
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add(rsi, rcx)
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add(rsi, rcx)
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lea(mem(rcx, rdi, 2), rdx) // c11_2 = c11 + 2*cs_c;
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// iteration 0
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movddup(mem(3+3*4)*8(rax), xmm3) // load xmm3 = (1/alpha33)
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#ifdef BLIS_ENABLE_TRSM_PREINVERSION
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mulpd(xmm3, xmm11) // xmm11 *= (1/alpha33);
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mulpd(xmm3, xmm15) // xmm15 *= (1/alpha33);
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#else
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divpd(xmm3, xmm11) // xmm11 /= alpha33;
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divpd(xmm3, xmm15) // xmm15 /= alpha33;
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#endif
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movaps(xmm11, mem(rbx, 6*16)) // store ( beta30 beta31 ) = xmm11
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movaps(xmm15, mem(rbx, 7*16)) // store ( beta32 beta33 ) = xmm15
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movlpd(xmm11, mem(rcx)) // store ( gamma30 ) = xmm11[0]
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movhpd(xmm11, mem(rcx, rdi, 1)) // store ( gamma31 ) = xmm11[1]
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movlpd(xmm15, mem(rdx)) // store ( gamma32 ) = xmm15[0]
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movhpd(xmm15, mem(rdx, rdi, 1)) // store ( gamma33 ) = xmm15[1]
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sub(rsi, rcx) // c11 -= rs_c
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sub(rsi, rdx) // c11_2 -= rs_c
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// iteration 1
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movddup(mem(2+2*4)*8(rax), xmm2) // load xmm2 = (1/alpha22)
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movddup(mem(2+3*4)*8(rax), xmm3) // load xmm3 = alpha23
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movaps(xmm3, xmm7) // xmm7 = xmm3
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mulpd(xmm11, xmm3) // xmm3 = alpha23 * ( beta30 beta31 )
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mulpd(xmm15, xmm7) // xmm7 = alpha23 * ( beta32 beta33 )
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subpd(xmm3, xmm10) // xmm10 -= xmm3
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subpd(xmm7, xmm14) // xmm14 -= xmm7
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#ifdef BLIS_ENABLE_TRSM_PREINVERSION
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mulpd(xmm2, xmm10) // xmm10 *= (1/alpha22);
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mulpd(xmm2, xmm14) // xmm14 *= (1/alpha22);
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#else
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divpd(xmm2, xmm10) // xmm10 /= alpha22;
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divpd(xmm2, xmm14) // xmm14 /= alpha22;
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#endif
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movaps(xmm10, mem(rbx, 4*16)) // store ( beta20 beta21 ) = xmm10
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movaps(xmm14, mem(rbx, 5*16)) // store ( beta22 beta23 ) = xmm14
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movlpd(xmm10, mem(rcx)) // store ( gamma20 ) = xmm10[0]
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movhpd(xmm10, mem(rcx, rdi, 1)) // store ( gamma21 ) = xmm10[1]
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movlpd(xmm14, mem(rdx)) // store ( gamma22 ) = xmm14[0]
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movhpd(xmm14, mem(rdx, rdi, 1)) // store ( gamma23 ) = xmm14[1]
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sub(rsi, rcx) // c11 -= rs_c
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sub(rsi, rdx) // c11_2 -= rs_c
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// iteration 2
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movddup(mem(1+1*4)*8(rax), xmm1) // load xmm1 = (1/alpha11)
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movddup(mem(1+2*4)*8(rax), xmm2) // load xmm2 = alpha12
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movddup(mem(1+3*4)*8(rax), xmm3) // load xmm3 = alpha13
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movaps(xmm2, xmm6) // xmm6 = xmm2
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movaps(xmm3, xmm7) // xmm7 = xmm3
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mulpd(xmm10, xmm2) // xmm2 = alpha12 * ( beta20 beta21 )
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mulpd(xmm14, xmm6) // xmm6 = alpha12 * ( beta22 beta23 )
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mulpd(xmm11, xmm3) // xmm3 = alpha13 * ( beta30 beta31 )
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mulpd(xmm15, xmm7) // xmm7 = alpha13 * ( beta32 beta33 )
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addpd(xmm3, xmm2) // xmm2 += xmm3;
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addpd(xmm7, xmm6) // xmm6 += xmm7;
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subpd(xmm2, xmm9) // xmm9 -= xmm2
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subpd(xmm6, xmm13) // xmm13 -= xmm6
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#ifdef BLIS_ENABLE_TRSM_PREINVERSION
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mulpd(xmm1, xmm9) // xmm9 *= (1/alpha11);
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mulpd(xmm1, xmm13) // xmm13 *= (1/alpha11);
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#else
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divpd(xmm1, xmm9) // xmm9 /= alpha11;
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divpd(xmm1, xmm13) // xmm13 /= alpha11;
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#endif
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movaps(xmm9, mem(rbx, 2*16)) // store ( beta10 beta11 ) = xmm9
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movaps(xmm13, mem(rbx, 3*16)) // store ( beta12 beta13 ) = xmm13
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movlpd(xmm9, mem(rcx)) // store ( gamma10 ) = xmm9[0]
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movhpd(xmm9, mem(rcx, rdi, 1)) // store ( gamma11 ) = xmm9[1]
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movlpd(xmm13, mem(rdx)) // store ( gamma12 ) = xmm13[0]
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movhpd(xmm13, mem(rdx, rdi, 1)) // store ( gamma13 ) = xmm13[1]
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sub(rsi, rcx) // c11 -= rs_c
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sub(rsi, rdx) // c11_2 -= rs_c
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// iteration 3
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movddup(mem(0+0*4)*8(rax), xmm0) // load xmm0 = (1/alpha00)
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movddup(mem(0+1*4)*8(rax), xmm1) // load xmm1 = alpha01
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movddup(mem(0+2*4)*8(rax), xmm2) // load xmm2 = alpha02
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movddup(mem(0+3*4)*8(rax), xmm3) // load xmm3 = alpha03
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movaps(xmm1, xmm5) // xmm5 = xmm1
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movaps(xmm2, xmm6) // xmm6 = xmm2
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movaps(xmm3, xmm7) // xmm7 = xmm3
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mulpd(xmm9, xmm1) // xmm1 = alpha01 * ( beta10 beta11 )
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mulpd(xmm13, xmm5) // xmm5 = alpha01 * ( beta12 beta13 )
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mulpd(xmm10, xmm2) // xmm2 = alpha02 * ( beta20 beta21 )
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mulpd(xmm14, xmm6) // xmm6 = alpha02 * ( beta22 beta23 )
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mulpd(xmm11, xmm3) // xmm3 = alpha03 * ( beta30 beta31 )
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mulpd(xmm15, xmm7) // xmm7 = alpha03 * ( beta32 beta33 )
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addpd(xmm2, xmm1) // xmm1 += xmm2;
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addpd(xmm6, xmm5) // xmm5 += xmm6;
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addpd(xmm3, xmm1) // xmm1 += xmm3;
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addpd(xmm7, xmm5) // xmm5 += xmm7;
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subpd(xmm1, xmm8) // xmm8 -= xmm1
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subpd(xmm5, xmm12) // xmm12 -= xmm5
|
|
#ifdef BLIS_ENABLE_TRSM_PREINVERSION
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|
mulpd(xmm0, xmm8) // xmm8 *= (1/alpha00);
|
|
mulpd(xmm0, xmm12) // xmm12 *= (1/alpha00);
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|
#else
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|
divpd(xmm0, xmm8) // xmm8 /= alpha00;
|
|
divpd(xmm0, xmm12) // xmm12 /= alpha00;
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|
#endif
|
|
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movaps(xmm8, mem(rbx, 0*16)) // store ( beta00 beta01 ) = xmm8
|
|
movaps(xmm12, mem(rbx, 1*16)) // store ( beta02 beta03 ) = xmm12
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|
movlpd(xmm8, mem(rcx)) // store ( gamma00 ) = xmm8[0]
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|
movhpd(xmm8, mem(rcx, rdi, 1)) // store ( gamma01 ) = xmm8[1]
|
|
movlpd(xmm12, mem(rdx)) // store ( gamma02 ) = xmm12[0]
|
|
movhpd(xmm12, mem(rdx, rdi, 1)) // store ( gamma03 ) = xmm12[1]
|
|
|
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end_asm(
|
|
: // output operands (none)
|
|
: // input operands
|
|
[k_iter] "m" (k_iter), // 0
|
|
[k_left] "m" (k_left), // 1
|
|
[a12] "m" (a12), // 2
|
|
[a11] "m" (a11), // 3
|
|
[b21] "m" (b21), // 4
|
|
[b11] "m" (b11), // 5
|
|
[c11] "m" (c11), // 6
|
|
[rs_c] "m" (rs_c), // 7
|
|
[cs_c] "m" (cs_c), // 8
|
|
[alpha] "m" (alpha), // 9
|
|
[b_next] "m" (b_next) // 10
|
|
: // register clobber list
|
|
"rax", "rbx", "rcx", "rdx", "rsi", "rdi",
|
|
"xmm0", "xmm1", "xmm2", "xmm3",
|
|
"xmm4", "xmm5", "xmm6", "xmm7",
|
|
"xmm8", "xmm9", "xmm10", "xmm11",
|
|
"xmm12", "xmm13", "xmm14", "xmm15",
|
|
"memory"
|
|
)
|
|
|
|
}
|
|
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|