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blis/kernels/zen/1
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Eleni Vlachopoulou 13aa3c8cd0 Adding AVX2 support for SNRM2 and SCNRM2 
- For the cases where AVX2 is available, an optimized function is called,
    based on Blue's algorithm. The fallback method based on sumsqv is used
    otherwise.

    - Scaling is used to avoid overflow and underflow.

    - Works correctly for negative increments.

    AMD-Internal: [SWLCSG-1080]

Change-Id: I6bf2f42652ba6b8a8631a0a9e6f6297d5b3ea5d9
2022-12-14 04:25:45 -05:00
..
bli_amaxv_zen_int.c
Added support for AVX512 for Windows and AMAVX
2022-06-08 11:09:48 +05:30
bli_axpbyv_zen_int10.c
Optimized AXPBYV Kernel using AVX2 Intrinsics
2022-01-05 04:19:11 -05:00
bli_axpbyv_zen_int.c
Optimized AXPBYV Kernel using AVX2 Intrinsics
2022-01-05 04:19:11 -05:00
bli_axpyv_zen_int10.c
Improved AXPYV Kernel performance
2021-12-20 13:21:20 +05:30
bli_axpyv_zen_int.c
This check in has changes w.r.t Copyright information, which is changed to (start year) - 2019
2019-05-27 16:24:43 +05:30
bli_copyv_zen_int.c
Squash-merge 'pr' into 'squash'. (#457)
2020-11-14 09:39:48 -06:00
bli_dotv_zen_int10.c
BLIS:merge:
2021-04-27 11:09:48 +05:30
bli_dotv_zen_int.c
Rebased amd-staging-milan-3.0 branch on master
2020-08-06 10:09:29 +05:30
bli_dotxv_zen_int.c
Implemented optimal dotxv kernel
2022-05-17 18:10:39 +05:30
bli_norm2_zen_int.c
Adding AVX2 support for SNRM2 and SCNRM2
2022-12-14 04:25:45 -05:00
bli_scalv_zen_int10.c
Vectorized and parallelized zdscal routine
2022-09-30 06:11:07 -04:00
bli_scalv_zen_int.c
This check in has changes w.r.t Copyright information, which is changed to (start year) - 2019
2019-05-27 16:24:43 +05:30
bli_setv_zen_int.c
Squash-merge 'pr' into 'squash'. (#457)
2020-11-14 09:39:48 -06:00
bli_swapv_zen_int8.c
BLIS:merge:
2021-04-27 11:09:48 +05:30
CMakeLists.txt
Copyright modification
2022-10-14 12:43:35 +05:30