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https://github.com/amd/blis.git
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Introduced support for GEMV operations with group-level symmetric quantization for the S8S8S32032 API. Framework Changes: - Added macro definitions and function prototypes for GEMV with symmetric quantization in lpgemm_5loop_interface_apis.h and lpgemm_kernels.h. - LPGEMV_M_EQ1_KERN2 for the lpgemv_m_one_s8s8s32os32_sym_quant kernel, and - LPGEMV_N_EQ1_KERN2 for the lpgemv_n_one_s8s8s32os32_sym_quant kernel. - Implemented the main GEMV framework for symmetric quantization in lpgemm_s8s8s32_sym_quant.c. Kernel Changes: - lpgemv_m_one_s8s8s32os32_sym_quant for handling the case where M = 1 and implemented in lpgemv_m_kernel_s8_grp_amd512vnni.c. - lpgemv_n_one_s8s8s32os32_sym_quant for handling the case where N = 1 and implemented in lpgemv_n_kernel_s8_grp_amd512vnni.c. - Updated the buffer reordering logic for group quantization for N=1 cases in aocl_gemm_s8s8s32os32_utils.c. Notes - Ensure that group_size is a factor of both K (and KC when K > KC). - The B matrix must be provided in reordered format (mtag_b == REORDERED). AMD-Internal: [SWLCSG-3604]
504 lines
13 KiB
C
504 lines
13 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2023 - 2025, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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#include "aocl_gemm_interface_apis.h"
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#include "lpgemm_types.h"
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#include "lpgemm_config.h"
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#include "lpgemm_utils_s8.h"
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#include "lpgemm_reorder_s8.h"
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AOCL_GEMM_GET_REORDER_BUF_SIZE(s8s8s32os32)
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{
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if ( ( k <= 0 ) || ( n <= 0 ) )
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{
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return 0; // Error.
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}
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// Check if avx512_vnni ISA is supported, lpgemm matmul only works with it.
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if ( bli_cpuid_is_avx512vnni_supported() == FALSE )
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{
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bli_print_msg(" AVX512_VNNI ISA not supported by processor, "
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"cannot perform s8s8s32 gemm.", __FILE__, __LINE__ );
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return 0; // Error.
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}
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/* Initialize BLIS. */
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bli_init_auto();
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// Set MC, NC, KC, NR, MR.
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aocl_lpgemm_init_global_cntx();
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AOCL_MATRIX_TYPE input_mat_type;
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bli_param_map_char_to_lpmat_type( mat_type, &input_mat_type );
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if ( input_mat_type == A_MATRIX )
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{
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return 0; // A reorder not supported.
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}
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// Extra space since packing does width in multiples of 16. The vnni
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// instruction can be used as long as atleast one zmm register can be fully
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// loaded; and since k_dim needs to be atleast 4, having n_dim atleast 16
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// should give 4x16=64 elements, enough for 1 zmm register.The padding is
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// not rounded to NR (=64), since that would result in memory wastage.
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#ifdef BLIS_KERNELS_ZEN4
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dim_t n_reorder;
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if( n == 1 )
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{
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n_reorder = 1;
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}
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else
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{
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n_reorder = make_multiple_of_n( n, 16 );
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}
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// Extra space since packing does length in multiples of 4.
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dim_t k_reorder;
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if( n == 1 )
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{
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k_reorder = k;
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}
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else
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{
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k_reorder = make_multiple_of_n( k, 4 );
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}
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#else
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dim_t n_reorder = make_multiple_of_n( n, 16 );
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dim_t k_reorder = make_multiple_of_n( k, 4 );
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#endif
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//extra memory of n_reorder * sizeof(int32_t) to store sum of every column of B matrix buffer
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siz_t size_req = sizeof( int8_t ) * k_reorder * n_reorder + ( n_reorder * sizeof( int32_t ) );
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return size_req;
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}
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AOCL_GEMM_GET_REORDER_BUF_SIZE_SYM_QUANT(s8s8s32os32_sym_quant)
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{
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if ( ( k <= 0 ) || ( n <= 0 ) )
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{
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return 0; // Error.
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}
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// Check if avx512_vnni ISA is supported, lpgemm matmul only works with it.
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if ( bli_cpuid_is_avx512vnni_supported() == FALSE )
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{
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bli_print_msg(" AVX512_VNNI ISA not supported by processor, "
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"cannot perform s8s8s32 gemm.", __FILE__, __LINE__ );
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return 0; // Error.
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}
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/* Initialize BLIS. */
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bli_init_auto();
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// Set MC, NC, KC, NR, MR.
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aocl_lpgemm_init_global_cntx();
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AOCL_MATRIX_TYPE input_mat_type;
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bli_param_map_char_to_lpmat_type( mat_type, &input_mat_type );
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if ( input_mat_type == A_MATRIX )
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{
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return 0; // A reorder not supported.
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}
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// Extra space since packing does width in multiples of 16. The vnni
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// instruction can be used as long as atleast one zmm register can be fully
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// loaded; and since k_dim needs to be atleast 4, having n_dim atleast 16
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// should give 4x16=64 elements, enough for 1 zmm register.The padding is
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// not rounded to NR (=64), since that would result in memory wastage.
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#ifdef BLIS_KERNELS_ZEN4
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dim_t n_reorder;
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if( n == 1 )
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{
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n_reorder = 1;
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}
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else
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{
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n_reorder = make_multiple_of_n( n, 16 );
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}
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// Extra space since packing does length in multiples of 4.
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dim_t k_reorder;
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if( n == 1 )
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{
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k_reorder = k;
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}
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else
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{
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k_reorder = make_multiple_of_n( k, 4 );
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}
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#else
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dim_t n_reorder = make_multiple_of_n( n, 16 );
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dim_t k_reorder = make_multiple_of_n( k, 4 );
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#endif
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dim_t group_size = meta_data->group_size;
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if( group_size & 3 )
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{
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bli_print_msg(" Group size should be multiple of 4 for s8s8s32os32_sym_quant", __FILE__, __LINE__ );
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return 0; // Error.
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}
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dim_t num_groups = ( k + group_size - 1 ) / group_size;
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// extra memory to store sum of every column per group of B matrix buffer
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size_t extra_mem_req = num_groups * n_reorder * sizeof( int32_t );
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//extra memory of n_reorder * sizeof(int32_t) to store sum of every column of B matrix buffer
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siz_t size_req = sizeof( int8_t ) * k_reorder * n_reorder + extra_mem_req;
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return size_req;
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}
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AOCL_GEMM_REORDER(int8_t,s8s8s32os32)
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{
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trans_t blis_trans;
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/* Map BLAS chars to their corresponding BLIS enumerated type value. */
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bli_param_map_netlib_to_blis_trans(trans, &blis_trans);
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if ((input_buf_addr == NULL) || (reorder_buf_addr == NULL) ||
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(k <= 0) || (n <= 0) )
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{
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return; // Error.
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}
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inc_t rs_b, cs_b;
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if( ( order == 'r') || ( order == 'R' ) )
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{
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if( ( bli_is_notrans( blis_trans ) && ( ldb < n ) ) ||
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( bli_is_trans( blis_trans ) && ( ldb < k ) ) )
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{
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return; // Error.
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}
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else
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{
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rs_b = bli_is_notrans( blis_trans ) ? ldb : 1;
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cs_b = bli_is_notrans( blis_trans ) ? 1 : ldb;
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}
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}
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else if ( ( order == 'c' ) || ( order == 'C' ) )
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{
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if( ( bli_is_notrans( blis_trans ) && ( ldb < k ) ) ||
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( bli_is_trans( blis_trans ) && ( ldb < n ) ) )
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{
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return; // Error.
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}
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else
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{
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rs_b = bli_is_notrans( blis_trans ) ? 1 : ldb;
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cs_b = bli_is_notrans( blis_trans ) ? ldb : 1;
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}
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}
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else
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{
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return; // Error
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}
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// Check if avx512_vnni ISA is supported, lpgemm matmul only works with it.
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if ( bli_cpuid_is_avx512vnni_supported() == FALSE )
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{
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bli_print_msg(" AVX512_VNNI ISA not supported by processor, "
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"cannot perform s8s8s32 gemm.", __FILE__, __LINE__ );
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return; // Error.
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}
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/* Initialize BLIS. */
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bli_init_auto();
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// Set MC, NC, KC, NR, MR.
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aocl_lpgemm_init_global_cntx();
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AOCL_MATRIX_TYPE input_mat_type;
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bli_param_map_char_to_lpmat_type( mat_type, &input_mat_type );
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if ( input_mat_type == A_MATRIX )
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{
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return; // A reorder not supported.
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}
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#ifdef BLIS_KERNELS_ZEN4
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if( n == 1 )
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{
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int32_t* pack_b_column_sum = ( int32_t* ) ( reorder_buf_addr +
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( sizeof( int8_t ) * n * k ));
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*pack_b_column_sum = 0;
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for( dim_t k0 = 0; k0 < k; k0++ )
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{
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reorder_buf_addr[k0] = input_buf_addr[ k0 * rs_b ];
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*pack_b_column_sum += reorder_buf_addr[k0];
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}
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*pack_b_column_sum *= 128;
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return;
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}
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#endif
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// Initialize a local runtime with global settings if necessary. Note
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// that in the case that a runtime is passed in, we make a local copy.
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rntm_t rntm_g;
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bli_rntm_init_from_global( &rntm_g );
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bli_pba_rntm_set_pba( &rntm_g );
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lpgemm_cntx_t* lcntx_g = lpgemm_get_global_cntx_obj( S8S8S32OS32 );
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// Create dummy b_reorder obj.
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lpgemm_obj_t b_reorder;
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b_reorder.storage.aligned_buffer = reorder_buf_addr;
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// Create dummy original b obj;
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lpgemm_obj_t b;
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b.storage.aligned_buffer = ( void* )input_buf_addr;
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b.rs = rs_b;
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b.cs = cs_b;
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b.width = n;
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b.length = k;
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reorderb_nr64_s8s8s32o32( &b, &b_reorder, &rntm_g, lcntx_g );
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}
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AOCL_GEMM_REORDER_SYM_QUANT(int8_t,s8s8s32os32_sym_quant)
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{
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trans_t blis_trans;
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/* Map BLAS chars to their corresponding BLIS enumerated type value. */
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bli_param_map_netlib_to_blis_trans(trans, &blis_trans);
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if ((input_buf_addr == NULL) || (reorder_buf_addr == NULL) ||
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(k <= 0) || (n <= 0) )
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{
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return; // Error.
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}
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inc_t rs_b, cs_b;
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if( ( order == 'r') || ( order == 'R' ) )
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{
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if( ( bli_is_notrans( blis_trans ) && ( ldb < n ) ) ||
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( bli_is_trans( blis_trans ) && ( ldb < k ) ) )
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{
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return; // Error.
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}
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else
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{
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rs_b = bli_is_notrans( blis_trans ) ? ldb : 1;
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cs_b = bli_is_notrans( blis_trans ) ? 1 : ldb;
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}
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}
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else if ( ( order == 'c' ) || ( order == 'C' ) )
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{
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if( ( bli_is_notrans( blis_trans ) && ( ldb < k ) ) ||
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( bli_is_trans( blis_trans ) && ( ldb < n ) ) )
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{
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return; // Error.
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}
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else
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{
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rs_b = bli_is_notrans( blis_trans ) ? 1 : ldb;
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cs_b = bli_is_notrans( blis_trans ) ? ldb : 1;
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}
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}
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else
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{
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return; // Error
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}
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// Check if avx512_vnni ISA is supported, lpgemm matmul only works with it.
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if ( bli_cpuid_is_avx512vnni_supported() == FALSE )
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{
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bli_print_msg(" AVX512_VNNI ISA not supported by processor, "
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"cannot perform s8s8s32 gemm.", __FILE__, __LINE__ );
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return; // Error.
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}
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dim_t group_size = meta_data->group_size;
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if( group_size & 3 )
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{
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bli_print_msg(" Group size should be multiple of 4 for s8s8s32os32_sym_quant", __FILE__, __LINE__ );
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return; // Error.
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}
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/* Initialize BLIS. */
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bli_init_auto();
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// Set MC, NC, KC, NR, MR.
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aocl_lpgemm_init_global_cntx();
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AOCL_MATRIX_TYPE input_mat_type;
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bli_param_map_char_to_lpmat_type( mat_type, &input_mat_type );
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if ( input_mat_type == A_MATRIX )
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{
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return; // A reorder not supported.
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}
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#ifdef BLIS_KERNELS_ZEN4
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if( n == 1 )
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{
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// Calculate the address of the beginning of the column sum buffer that
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// is allocated after the reorder buffer.
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int32_t* pack_b_column_sum = ( int32_t* ) ( reorder_buf_addr +
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( k * sizeof( int8_t ) ) );
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// NOTE We're working under the assumption that group_size is a factor
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// of k.
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for ( dim_t k0 = 0; k0 < k; k0 += group_size )
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{
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// Initialize the current column sum to 0.
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*pack_b_column_sum = 0;
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for ( dim_t group = 0; group < group_size; group++ )
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{
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reorder_buf_addr[ k0 + group ] = input_buf_addr[ ( k0 + group ) * rs_b ];
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*pack_b_column_sum += reorder_buf_addr[ k0 + group ];
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}
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*pack_b_column_sum *= 128;
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// Move the pack_b_column_sum pointer one step to the next group.
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pack_b_column_sum += 1;
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}
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return;
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}
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#endif
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// Initialize a local runtime with global settings if necessary. Note
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// that in the case that a runtime is passed in, we make a local copy.
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rntm_t rntm_g;
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bli_rntm_init_from_global( &rntm_g );
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bli_pba_rntm_set_pba( &rntm_g );
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lpgemm_cntx_t* lcntx_g = lpgemm_get_global_cntx_obj( S8S8S32OS32 );
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// Create dummy b_reorder obj.
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lpgemm_obj_t b_reorder;
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b_reorder.storage.aligned_buffer = reorder_buf_addr;
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// Create dummy original b obj;
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lpgemm_obj_t b;
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b.storage.aligned_buffer = ( void* )input_buf_addr;
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b.rs = rs_b;
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b.cs = cs_b;
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b.width = n;
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b.length = k;
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reorderb_nr64_s8s8s32o32_sym_quant( &b, &b_reorder, &rntm_g, lcntx_g, group_size );
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}
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AOCL_GEMM_UNREORDER(int8_t, s8s8s32os32_reference)
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{
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if ( ( output_buf_addr == NULL ) || ( reorder_buf_addr == NULL ) ||
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( k <= 0 ) || ( n <= 0 ) )
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{
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return; // Error.
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}
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inc_t rs_b, cs_b;
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// Check for the validity of strides.
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if( ( order == 'r' ) || ( order == 'R' ) )
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{
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if( ldb < n ) return; // Error
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else
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{
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rs_b = ldb;
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cs_b = 1;
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}
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}
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else if( ( order == 'c' ) || ( order == 'C' ) )
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{
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if( ldb < k ) return; // Error.
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else
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{
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rs_b = 1;
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cs_b = ldb;
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}
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}
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else
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{
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return; // Error.
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}
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/* Initialize BLIS. */
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bli_init_auto();
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// Set MC, NC, KC, NR, MR.
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aocl_lpgemm_init_global_cntx();
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AOCL_MATRIX_TYPE input_mat_type;
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bli_param_map_char_to_lpmat_type( mat_type, &input_mat_type );
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if ( input_mat_type == A_MATRIX )
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{
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return; // A reorder not supported.
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}
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#ifdef BLIS_KERNELS_ZEN4
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if( n == 1 )
|
|
{
|
|
if( rs_b == 1 )
|
|
{
|
|
memcpy( output_buf_addr, reorder_buf_addr, ( k * sizeof( int8_t ) ) );
|
|
}
|
|
else
|
|
{
|
|
for( dim_t k0 = 0; k0 < k; k0++ )
|
|
{
|
|
output_buf_addr[k0*rs_b] = reorder_buf_addr[k0];
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
// Initialize a local runtime with global settings if necessary. Note
|
|
// that in the case that a runtime is passed in, we make a local copy.
|
|
rntm_t rntm_g;
|
|
bli_rntm_init_from_global( &rntm_g );
|
|
bli_pba_rntm_set_pba( &rntm_g );
|
|
|
|
lpgemm_cntx_t* lcntx_g = lpgemm_get_global_cntx_obj( S8S8S32OS32 );
|
|
|
|
// Create dummy b_reorder obj.
|
|
lpgemm_obj_t b_reorder;
|
|
b_reorder.storage.aligned_buffer = ( void* ) reorder_buf_addr;
|
|
|
|
// Create dummy original b obj;
|
|
lpgemm_obj_t b;
|
|
b.storage.aligned_buffer = ( void* )output_buf_addr;
|
|
b.rs = rs_b;
|
|
b.cs = cs_b;
|
|
b.width = n;
|
|
b.length = k;
|
|
|
|
unreorderb_nr64_s8s8s32os32_reference( &b, &b_reorder, &rntm_g, lcntx_g );
|
|
} |