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76c4872718
Introduced support for GEMV operations with group-level symmetric quantization for the S8S8S32032 API. Framework Changes: - Added macro definitions and function prototypes for GEMV with symmetric quantization in lpgemm_5loop_interface_apis.h and lpgemm_kernels.h. - LPGEMV_M_EQ1_KERN2 for the lpgemv_m_one_s8s8s32os32_sym_quant kernel, and - LPGEMV_N_EQ1_KERN2 for the lpgemv_n_one_s8s8s32os32_sym_quant kernel. - Implemented the main GEMV framework for symmetric quantization in lpgemm_s8s8s32_sym_quant.c. Kernel Changes: - lpgemv_m_one_s8s8s32os32_sym_quant for handling the case where M = 1 and implemented in lpgemv_m_kernel_s8_grp_amd512vnni.c. - lpgemv_n_one_s8s8s32os32_sym_quant for handling the case where N = 1 and implemented in lpgemv_n_kernel_s8_grp_amd512vnni.c. - Updated the buffer reordering logic for group quantization for N=1 cases in aocl_gemm_s8s8s32os32_utils.c. Notes - Ensure that group_size is a factor of both K (and KC when K > KC). - The B matrix must be provided in reordered format (mtag_b == REORDERED). AMD-Internal: [SWLCSG-3604]
330 lines
11 KiB
C
330 lines
11 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LPGEMM_5LOOP_INTF_H
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#define LPGEMM_5LOOP_INTF_H
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#include "lpgemm_types.h"
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#include "lpgemm_post_ops.h"
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#include "aocl_bf16_type.h"
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#define LPGEMM_TINY(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_tiny_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_TINY(float,float,float,f32f32f32of32);
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LPGEMM_TINY(bfloat16,bfloat16,float,bf16bf16f32of32);
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#define LPGEMM_5LOOP(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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dim_t rs_b, \
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dim_t cs_b, \
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AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP(uint8_t,int8_t,int32_t,u8s8s32o32);
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LPGEMM_5LOOP(float,float,float,f32f32f32of32);
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LPGEMM_5LOOP(bfloat16,bfloat16,float,bf16bf16f32of32);
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LPGEMM_5LOOP(int8_t,int8_t,int32_t,s8s8s32o32);
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#define LPGEMM_5LOOP1(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_pre_op* pre_op_list, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP1(bfloat16,int8_t,float,bf16s4f32of32);
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#define LPGEMM_5LOOP2(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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float* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_group_post_op* grp_post_op_list, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP2(int8_t,int8_t,int32_t,s8s8s32o32_sym_quant);
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#define LPGEMM_5LOOP_AVX2(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_avx2_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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dim_t rs_b, \
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dim_t cs_b, \
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AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP_AVX2(bfloat16,bfloat16,float,bf16bf16f32of32);
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#define LPGEMM_5LOOP_AVX512BF16(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_avx512bf16_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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dim_t rs_b, \
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dim_t cs_b, \
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AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP_AVX512BF16(bfloat16,bfloat16,float,bf16bf16f32of32);
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#define LPGEMV_TINY(A_type, B_type, C_type, LP_SFX) \
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void lpgemv_rowvar_tiny_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type *a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type *b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type *c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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lpgemm_cntx_t *lcntx, \
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lpgemm_post_op *post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMV_TINY(float, float, float, f32f32f32of32);
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LPGEMV_TINY(bfloat16,bfloat16,float,bf16bf16f32of32);
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#define LPGEMV(A_type, B_type, C_type, LP_SFX) \
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void lpgemv_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type *a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type *b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type *c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t *rntm, \
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lpgemm_thrinfo_t *thread, \
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lpgemm_cntx_t *lcntx, \
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lpgemm_post_op *post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMV(float, float, float, f32f32f32of32);
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LPGEMV(bfloat16,bfloat16,float,bf16bf16f32of32);
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LPGEMV(uint8_t,int8_t,int32_t,u8s8s32os32);
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LPGEMV(int8_t,int8_t,int32_t,s8s8s32os32);
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#define LPGEMV_AVX2(A_type, B_type, C_type, LP_SFX) \
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void lpgemv_rowvar_avx2_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type *a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type *b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type *c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t *rntm, \
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lpgemm_thrinfo_t *thread, \
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lpgemm_cntx_t *lcntx, \
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lpgemm_post_op *post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMV_AVX2(bfloat16, bfloat16, float, bf16bf16f32of32);
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#define LPGEMV2(A_type, B_type, C_type, LP_SFX) \
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void lpgemv_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type *a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type *b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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float *c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t *rntm, \
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lpgemm_thrinfo_t *thread, \
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lpgemm_cntx_t *lcntx, \
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lpgemm_group_post_op *grp_post_op_list, \
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lpgemm_post_op *post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMV2(int8_t,int8_t,int32_t,s8s8s32os32_sym_quant);
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#endif // LPGEMM_5LOOP_INTF_H
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