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f032d5d4a6
Here adds two kernels for Arm SVE vector extensions. 1. a gemm kernel for double at sizes 8x8. 2. a packm kernel for double at dimension 8xk. To achive best performance, variable length agonostic programming is not used. Vector length (VL) of 256 bits is mandated in both kernels. Kernels to support other VLs can be added later. "SVE is a vector extension for AArch64 execution mode for the A64 instruction set of the Armv8 architecture. Unlike other SIMD architectures, SVE does not define the size of the vector registers, but constrains into a range of possible values, from a minimum of 128 bits up to a maximum of 2048 in 128-bit wide units. Therefore, any CPU vendor can implement the extension by choosing the vector register size that better suits the workloads the CPU is targeting. Instructions are provided specifically to query an implementation for its register size, to guarantee that the applications can run on different implementations of the ISA without the need to recompile the code." [1] [1] https://developer.arm.com/solutions/hpc/resources/hpc-white-papers/arm-scalable-vector-extensions-and-application-to-machine-learning Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
297 lines
6.5 KiB
C
297 lines
6.5 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2016, Hewlett Packard Enterprise Development LP
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Copyright (C) 2019, Advanced Micro Devices, Inc.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BLIS_ARCH_CONFIG_H
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#define BLIS_ARCH_CONFIG_H
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//
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// -- Context initialization prototypes ----------------------------------------
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//
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// -- Intel64 architectures --
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#ifdef BLIS_CONFIG_SKX
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CNTX_INIT_PROTS( skx )
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#endif
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#ifdef BLIS_CONFIG_KNL
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CNTX_INIT_PROTS( knl )
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#endif
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#ifdef BLIS_CONFIG_KNC
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CNTX_INIT_PROTS( knc )
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#endif
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#ifdef BLIS_CONFIG_HASWELL
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CNTX_INIT_PROTS( haswell )
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#endif
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#ifdef BLIS_CONFIG_SANDYBRIDGE
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CNTX_INIT_PROTS( sandybridge )
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#endif
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#ifdef BLIS_CONFIG_PENRYN
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CNTX_INIT_PROTS( penryn )
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#endif
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// -- AMD64 architectures --
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#ifdef BLIS_CONFIG_ZEN2
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CNTX_INIT_PROTS( zen2 )
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#endif
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#ifdef BLIS_CONFIG_ZEN
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CNTX_INIT_PROTS( zen )
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#endif
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#ifdef BLIS_CONFIG_EXCAVATOR
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CNTX_INIT_PROTS( excavator )
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#endif
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#ifdef BLIS_CONFIG_STEAMROLLER
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CNTX_INIT_PROTS( steamroller )
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#endif
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#ifdef BLIS_CONFIG_PILEDRIVER
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CNTX_INIT_PROTS( piledriver )
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#endif
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#ifdef BLIS_CONFIG_BULLDOZER
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CNTX_INIT_PROTS( bulldozer )
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#endif
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// -- ARM architectures --
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#ifdef BLIS_CONFIG_THUNDERX2
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CNTX_INIT_PROTS( thunderx2 )
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#endif
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#ifdef BLIS_CONFIG_CORTEXA57
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CNTX_INIT_PROTS( cortexa57 )
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#endif
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#ifdef BLIS_CONFIG_CORTEXA53
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CNTX_INIT_PROTS( cortexa53 )
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#endif
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#ifdef BLIS_CONFIG_CORTEXA15
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CNTX_INIT_PROTS( cortexa15 )
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#endif
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#ifdef BLIS_CONFIG_CORTEXA9
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CNTX_INIT_PROTS( cortexa9 )
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#endif
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// -- IBM Power --
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#ifdef BLIS_CONFIG_POWER9
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CNTX_INIT_PROTS( power9 )
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#endif
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#ifdef BLIS_CONFIG_POWER7
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CNTX_INIT_PROTS( power7 )
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#endif
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// -- IBM BG/Q --
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#ifdef BLIS_CONFIG_BGQ
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CNTX_INIT_PROTS( bgq )
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#endif
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// -- Generic --
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#ifdef BLIS_CONFIG_GENERIC
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CNTX_INIT_PROTS( generic )
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#endif
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//
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// -- Architecture family-specific headers -------------------------------------
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//
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// -- x86_64 families --
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#ifdef BLIS_FAMILY_INTEL64
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#include "bli_family_intel64.h"
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#endif
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#ifdef BLIS_FAMILY_AMD64
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#include "bli_family_amd64.h"
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#endif
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#ifdef BLIS_FAMILY_X86_64
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#include "bli_family_x86_64.h"
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#endif
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// -- Intel64 architectures --
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#ifdef BLIS_FAMILY_SKX
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#include "bli_family_skx.h"
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#endif
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#ifdef BLIS_FAMILY_KNL
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#include "bli_family_knl.h"
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#endif
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#ifdef BLIS_FAMILY_KNC
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#include "bli_family_knc.h"
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#endif
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#ifdef BLIS_FAMILY_HASWELL
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#include "bli_family_haswell.h"
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#endif
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#ifdef BLIS_FAMILY_SANDYBRIDGE
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#include "bli_family_sandybridge.h"
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#endif
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#ifdef BLIS_FAMILY_PENRYN
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#include "bli_family_penryn.h"
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#endif
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// -- AMD64 architectures --
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#ifdef BLIS_FAMILY_ZEN2
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#include "bli_family_zen2.h"
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#endif
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#ifdef BLIS_FAMILY_ZEN
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#include "bli_family_zen.h"
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#endif
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#ifdef BLIS_FAMILY_EXCAVATOR
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#include "bli_family_excavator.h"
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#endif
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#ifdef BLIS_FAMILY_STEAMROLLER
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#include "bli_family_steamroller.h"
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#endif
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#ifdef BLIS_FAMILY_PILEDRIVER
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#include "bli_family_piledriver.h"
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#endif
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#ifdef BLIS_FAMILY_BULLDOZER
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#include "bli_family_bulldozer.h"
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#endif
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// -- ARM architectures --
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#ifdef BLIS_FAMILY_THUNDERX2
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#include "bli_family_thunderx2.h"
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#endif
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#ifdef BLIS_FAMILY_CORTEXA57
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#include "bli_family_cortexa57.h"
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#endif
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#ifdef BLIS_FAMILY_CORTEXA53
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#include "bli_family_cortexa53.h"
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#endif
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#ifdef BLIS_FAMILY_CORTEXA15
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#include "bli_family_cortexa15.h"
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#endif
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#ifdef BLIS_FAMILY_CORTEXA9
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#include "bli_family_cortexa9.h"
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#endif
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// -- IBM Power --
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#ifdef BLIS_FAMILY_POWER9
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#include "bli_family_power9.h"
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#endif
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#ifdef BLIS_FAMILY_POWER7
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#include "bli_family_power7.h"
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#endif
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// -- IBM BG/Q --
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#ifdef BLIS_FAMILY_BGQ
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#include "bli_family_bgq.h"
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#endif
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// -- Generic --
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#ifdef BLIS_FAMILY_GENERIC
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#include "bli_family_generic.h"
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#endif
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//
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// -- kernel set prototypes ----------------------------------------------------
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//
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// -- Intel64 architectures --
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#ifdef BLIS_KERNELS_SKX
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#include "bli_kernels_skx.h"
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#endif
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#ifdef BLIS_KERNELS_KNL
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#include "bli_kernels_knl.h"
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#endif
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#ifdef BLIS_KERNELS_KNC
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#include "bli_kernels_knc.h"
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#endif
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#ifdef BLIS_KERNELS_HASWELL
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#include "bli_kernels_haswell.h"
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#endif
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#ifdef BLIS_KERNELS_SANDYBRIDGE
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#include "bli_kernels_sandybridge.h"
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#endif
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#ifdef BLIS_KERNELS_PENRYN
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#include "bli_kernels_penryn.h"
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#endif
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// -- AMD64 architectures --
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//#ifdef BLIS_KERNELS_ZEN2
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//#include "bli_kernels_zen2.h"
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//#endif
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#ifdef BLIS_KERNELS_ZEN
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#include "bli_kernels_zen.h"
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#endif
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//#ifdef BLIS_KERNELS_EXCAVATOR
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//#include "bli_kernels_excavator.h"
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//#endif
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//#ifdef BLIS_KERNELS_STEAMROLLER
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//#include "bli_kernels_steamroller.h"
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//#endif
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#ifdef BLIS_KERNELS_PILEDRIVER
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#include "bli_kernels_piledriver.h"
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#endif
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#ifdef BLIS_KERNELS_BULLDOZER
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#include "bli_kernels_bulldozer.h"
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#endif
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// -- ARM architectures --
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#ifdef BLIS_KERNELS_ARMSVE
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#include "bli_kernels_armsve.h"
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#endif
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#ifdef BLIS_KERNELS_ARMV8A
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#include "bli_kernels_armv8a.h"
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#endif
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#ifdef BLIS_KERNELS_ARMV7A
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#include "bli_kernels_armv7a.h"
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#endif
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// -- IBM Power --
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#ifdef BLIS_KERNELS_POWER9
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#include "bli_kernels_power9.h"
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#endif
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#ifdef BLIS_KERNELS_POWER7
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#include "bli_kernels_power7.h"
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#endif
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// -- IBM BG/Q --
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#ifdef BLIS_KERNELS_BGQ
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#include "bli_kernels_bgq.h"
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#endif
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#endif
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