Files
blis/kernels
Rayan, Rohan 825244052d SGEMM Zen5 RD kernel optimization
Removed function calls to 6x48, 6x32, 6x16, 6x8, 6x4 fringe kernels. These are now handled in the main kernel directly
Introduced new fringe kernels 6x3, 6x2 in the n-direction
Removed fringe kernel calls to AVX2 code path
Access pattern inside the kernel changed so that the C-matrix stores are along the cache line
Various instruction level optimizations
These kerels are enabled also on the Zen6 code path
Tiny path modified to take these newer kernels on zen5 and zen6
Added Gtests for these new kernels

AMD-Internal: CPUPL-8424, SWLCSG-3272
Co-authored-by: Rohan Rayan rohrayan@amd.com
2026-07-01 14:57:59 +05:30
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