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92fbd04238
- Introduced a new 24x8 column preferred DGEMM sup kernel for zen5. - A prefetch logic is modified compared to zen4 24x8 sup kernels. - Earlier, next panel of A is prefetched into L2 cache, which is now modified to prefetching the second next column of the current panel of A into L1 cache. - B and C prefetches are enabled and unchanged. - Tuned MC, KC and NC block sizes for new kernel. AMD-Internal: [CPUPL-5262] Change-Id: If933537e50f43f5560e0fe18a716aa1e36ced64d
For more information on sub-configurations and configuration families in BLIS, please read the Configuration Guide, which can be viewed in markdown-rendered form from the BLIS wiki page.
If you don't have time, or are impatient, take a look at the config_registry
file in the top-level directory of the BLIS distribution. It contains a
grammar-like mapping of configuration names, or families, to sub-configurations,
which may be other families. Keep in mind that the / notation:
<config>: <config>/<name>
means that the kernel set associated with <name> should be made available to
the configuration <config> if <config> is targeted at configure-time.
(Some configurations borrow kernels from other configurations, and this is how
we specify that requirement.)