Vignesh Balasubramanian 4ec2bad744 Updating reduction step of AVX512 DNRM2 API ...

- Updated the final reduction of partial sums to use scalar accumulation
  entirely, instead of using the _mm512_reduce_add_pd( ... ) intrinsic.
  This will in turn change the associativity and the rounding-off
  pattern in the reduction step.

- Defined a union data-type to do the same, by having a 512-bit
  register and a double-precision array as its members.

- Updated the declaration and usage of the register variable according
  to the union definition, for uniformity.

AMD-Internal: [CPUPL-5472]
Change-Id: I997464a6ec47e4054dca48a000fbd4ac0cfcc679

2024-08-01 17:09:17 +05:30

..

1

Updating reduction step of AVX512 DNRM2 API

2024-08-01 17:09:17 +05:30

1f

DGEMV Optimizations for NO_TRANSPOSE cases

2024-07-24 15:59:36 +05:30

1m

DGEMM optimizations for Turin Classic

2024-07-09 07:53:27 -04:00

3

Added 24x8 triangular kernels for DGEMMT SUP

2024-07-22 12:02:30 -04:00

aocl_smart

CMake: Adding new portable CMake system.

2023-11-09 15:49:45 +05:30

lpgemm

Fixing control flow in aocl_gemm_bf16s4f32of32|bf16

2024-07-29 05:12:09 -04:00

bli_kernels_zen4.h

DGEMV Optimizations for NO_TRANSPOSE cases

2024-07-24 15:59:36 +05:30