Ruchika Ashtankar 92fbd04238 DGEMM SUP Optimizations for Turin ...

- Introduced a new 24x8 column preferred DGEMM sup kernel for zen5.
- A prefetch logic is modified compared to zen4 24x8 sup kernels.
- Earlier, next panel of A is prefetched into L2 cache,
  which is now modified to prefetching the second next column
  of the current panel of A into L1 cache.
- B and C prefetches are enabled and unchanged.
- Tuned MC, KC and NC block sizes for new kernel.

AMD-Internal: [CPUPL-5262]
Change-Id: If933537e50f43f5560e0fe18a716aa1e36ced64d

2024-08-02 04:00:51 -04:00

..

sup

DGEMM SUP Optimizations for Turin

2024-08-02 04:00:51 -04:00

bli_dgemm_avx512_asm_8x24.c

DGEMM Native AVX512 updates

2024-07-31 12:23:34 -04:00