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04ae01aeab
Description: 1. The bias type was supported only based on output data type. 2. The option is added in the pre-ops structure to select the bias data type irrespective of the storage data type in bf16 and WoQ API's AMD-Internal: SWLCSG-3171 Change-Id: Iac10b946c2d4a5c405b2dc857362be0058615abf
111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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#include "lpgemm_eltwise_ops_interface_apis.h"
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#include "lpgemm_eltwise_ops_kernels.h"
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#include "lpgemm_utils.h"
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#include "lpgemm_thrinfo_utils.h"
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#include "lpgemm_config.h"
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// Kernel function prototypes.
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typedef void (*lpgemm_util_post_ops_kernel_f32)
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(
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const dim_t,
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const dim_t,
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const bfloat16*,
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const dim_t,
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const dim_t,
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float*,
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const dim_t,
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const dim_t,
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lpgemm_post_op*,
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lpgemm_post_op_attr
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);
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LPGEMM_ELTWISE_OPS_IFACE(bfloat16,float,bf16of32)
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{
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dim_t NR = lcntx->blksz.NR;
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dim_t MR = lcntx->blksz.MR;
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lpgemm_post_op_attr post_ops_attr;
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post_ops_attr.c_stor_type = c_downscale;
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post_ops_attr.bias_stor_type = (
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post_op_list->bias_stor_type != NONE ) ?
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post_op_list->bias_stor_type : c_downscale;
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post_ops_attr.buf_downscale = NULL;
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// Generate thrinfo objects for jc and ic loops from lpgemm_thrinfo_t.
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thrinfo_t thread_jc;
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thrinfo_t thread_ic;
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lpgemm_gen_thrinfo( thread, &thread_jc, &thread_ic );
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// Compute the JC, IC loop thread range for the current thread.
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dim_t jc_start, jc_end;
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bli_thread_range_sub( &thread_jc, n, NR, FALSE, &jc_start, &jc_end );
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dim_t ic_start, ic_end;
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bli_thread_range_sub( &thread_ic, m, MR, FALSE, &ic_start, &ic_end );
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post_ops_attr.post_op_c_i = ic_start;
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post_ops_attr.post_op_c_j = jc_start;
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post_ops_attr.rs_c_downscale = rs_b;
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post_ops_attr.cs_c_downscale = cs_b;
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post_ops_attr.is_first_k = FALSE;
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post_ops_attr.is_last_k = TRUE; // Should always be TRUE here.
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// Advance the matrix to the right positions based on thread id.
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// To note that float and bfloat16 are both handled using this same
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// frame, so the strides needs to be updated on the actual b matrix
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// datatype or the c_downscale value.
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dim_t dsize = sizeof( float );
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if ( post_ops_attr.c_stor_type == BF16 )
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{
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dsize = sizeof( bfloat16 );
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}
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int8_t* b_i = ( int8_t* )b;
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( ( lpgemm_util_post_ops_kernel_f32 )( lcntx->eltwise_ops_kern_fun_ptr ) )
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(
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( ic_end - ic_start ), ( jc_end - jc_start ),
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a + ( rs_a * ic_start ) + ( cs_a * jc_start ),
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rs_a, cs_a,
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( float* )( b_i + ( dsize * ( ( rs_b * ic_start ) +
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( cs_b * jc_start ) ) ) ), rs_b, cs_b,
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post_op_list, post_ops_attr
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);
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}
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