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bfc512d3e1
Details: - The batch matmul performs a series of matmuls, processing more than one GEMM problem at once. - Introduced a new parameter called batch_size for the user to indicate number of GEMM problems in a batch/group. - This operation supports processing GEMM problems with different parameters including dims,post-ops,stor-schemes etc., - This operation is optimized for problems where all the GEMMs in a batch are of same size and shape. - For now, the threads are distributed among different GEMM problems equally irrespective of their dimensions which leads to better performance for batches with identical GEMMs but performs sub-optimally for batches with non-identical GEMMs. - Optimizations for batches with non-identical GEMMs is in progress. - Added bench and input files for batch_matmul. AMD-Internal: [SWLCSG-2944] Change-Id: Idc59db5b8c5794bf19f6f86bcb8455cd2599c155
165 lines
5.9 KiB
C
165 lines
5.9 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LPGEMM_5LOOP_INTF_H
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#define LPGEMM_5LOOP_INTF_H
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#include "lpgemm_types.h"
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#include "lpgemm_post_ops.h"
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#include "aocl_bf16_type.h"
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#define LPGEMM_5LOOP(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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dim_t rs_b, \
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dim_t cs_b, \
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AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP(uint8_t,int8_t,int32_t,u8s8s32o32);
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LPGEMM_5LOOP(uint8_t,int8_t,int16_t,u8s8s16o16);
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LPGEMM_5LOOP(float,float,float,f32f32f32of32);
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LPGEMM_5LOOP(bfloat16,bfloat16,float,bf16bf16f32of32);
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LPGEMM_5LOOP(int8_t,int8_t,int32_t,s8s8s32o32);
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LPGEMM_5LOOP(int8_t,int8_t,int16_t,s8s8s16o16);
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#define BATCH_LPGEMM_5LOOP(A_type,B_type,C_type,LP_SFX) \
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void batch_lpgemm_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type** a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type** b, \
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dim_t rs_b, \
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dim_t cs_b, \
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AOCL_MEMORY_TAG mtag_b, \
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C_type** c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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BATCH_LPGEMM_5LOOP(bfloat16,bfloat16,float,bf16bf16f32of32);
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#define LPGEMM_5LOOP1(A_type,B_type,C_type,LP_SFX) \
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void lpgemm_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type* a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type* b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type* c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t* rntm, \
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lpgemm_thrinfo_t* thread, \
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lpgemm_cntx_t* lcntx, \
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lpgemm_pre_op* pre_op_list, \
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lpgemm_post_op* post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMM_5LOOP1(bfloat16,int8_t,float,bf16s4f32of32);
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#define LPGEMV(A_type, B_type, C_type, LP_SFX) \
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void lpgemv_rowvar_ ## LP_SFX \
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( \
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const dim_t m, \
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const dim_t n, \
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const dim_t k, \
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const A_type *a, \
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const dim_t rs_a, \
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const dim_t cs_a, \
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const AOCL_MEMORY_TAG mtag_a, \
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const B_type *b, \
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const dim_t rs_b, \
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const dim_t cs_b, \
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const AOCL_MEMORY_TAG mtag_b, \
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C_type *c, \
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const dim_t rs_c, \
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const dim_t cs_c, \
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const C_type alpha, \
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const C_type beta, \
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rntm_t *rntm, \
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lpgemm_thrinfo_t *thread, \
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lpgemm_cntx_t *lcntx, \
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lpgemm_post_op *post_op_list, \
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AOCL_STORAGE_TYPE c_downscale \
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) \
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LPGEMV(float, float, float, f32f32f32of32);
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LPGEMV(bfloat16,bfloat16,float,bf16bf16f32of32);
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LPGEMV(uint8_t,int8_t,int32_t,u8s8s32os32);
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LPGEMV(int8_t,int8_t,int32_t,s8s8s32os32);
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#endif // LPGEMM_5LOOP_INTF_H
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