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Description: --Added support for tranB in u8s8s32o<s32|s8> and s8s8s32o<s32|s8> API's --Updated the bench_lpgemm by adding options to support transpose of B matrix --Updated data_gen_script.py in lpgemm bench according to latest input format. AMD-Internal: [SWLCSG-2582] Change-Id: I4a05cc390ae11440d6ff86da281dbafbeb907048
225 lines
7.5 KiB
C
225 lines
7.5 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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#include "lpgemm_utils_s8.h"
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#include "lpgemm_reorder_s8.h"
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#include "lpgemm_packa_s8.h"
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#include "lpgemm_packb_s8.h"
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#include "lpgemm_config.h"
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void reorderb_nr64_s8s8s32o32
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(
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lpgemm_obj_t* b,
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lpgemm_obj_t* b_reorder,
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rntm_t* rntm,
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lpgemm_cntx_t* lcntx
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)
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{
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dim_t NC = lcntx->blksz.NC;
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dim_t KC = lcntx->blksz.KC;
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dim_t NR = lcntx->blksz.NR;
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dim_t rs_b = b->rs;
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dim_t cs_b = b->cs;
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dim_t rs_b_reorder;
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dim_t cs_b_reorder;
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dim_t n = b->width;
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dim_t k = b->length;
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// k needs to be a multiple of 4 so that it can be used with vpdpbusd
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// instruction. Padding is added in cases this condition is not
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// satisfied, and therefore the k offset used for packed/reordered
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// buffer needs to be updated.
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dim_t k_updated = make_multiple_of_n( k, 4 );
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dim_t n_updated = make_multiple_of_n( n, 16 );
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dim_t n_threads = bli_rntm_num_threads( rntm );
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n_threads = ( n_threads > 0 ) ? n_threads : 1;
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int32_t* pack_b_column_sum =
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( int32_t* ) ( b_reorder->storage.aligned_buffer +
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( sizeof( int8_t ) * n_updated * k_updated ));
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for ( dim_t idx = 0; idx < n_updated; idx++ )
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{
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*( pack_b_column_sum + idx ) = 0;
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}
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#ifdef BLIS_ENABLE_OPENMP
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_Pragma( "omp parallel num_threads(n_threads)" )
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{
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// Initialise a local thrinfo obj for work split across threads.
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thrinfo_t thread_jc;
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bli_thrinfo_set_n_way( n_threads, &thread_jc );
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bli_thrinfo_set_work_id( omp_get_thread_num(), &thread_jc );
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#else
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{
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// Initialise a local thrinfo obj for work split across threads.
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thrinfo_t thread_jc;
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bli_thrinfo_set_n_way( 1, &thread_jc );
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bli_thrinfo_set_work_id( 0, &thread_jc );
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#endif
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// Compute the JC loop thread range for the current thread.
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dim_t jc_start, jc_end;
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bli_thread_range_sub( &thread_jc, n, NR, FALSE, &jc_start, &jc_end );
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for ( dim_t jc = jc_start; jc < jc_end; jc += NC )
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{
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dim_t nc0 = bli_min( ( jc_end - jc ), NC );
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dim_t jc_cur_loop = jc;
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dim_t jc_cur_loop_rem = 0;
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dim_t n_sub_updated;
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get_B_panel_reordered_start_offset_width
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(
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jc, n, NC, get_packb_s8s8s32o32_min_NR(),
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&jc_cur_loop, &jc_cur_loop_rem,
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&nc0, &n_sub_updated
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);
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for ( dim_t pc = 0; pc < k; pc += KC )
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{
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dim_t kc0 = bli_min( ( k - pc ), KC );
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// kc0 needs to be a multiple of 4 so that it can be used with
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// vpdpbusd instruction. Padding is added in cases this
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// condition is not satisfied, and therefore the kc0 offsets
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// used for packed/reordered buffers needs to be updated.
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dim_t kc0_updated = make_multiple_of_n( kc0, 4 );
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// The offsets are calculated in such a way that it resembles
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// the reorder buffer traversal in single threaded reordering.
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// The panel boundaries (KCxNC) remain as it is accessed in
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// single thread, and as a consequence a thread with jc_start
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// inside the panel cannot consider NC range for reorder. It
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// has to work with NC' < NC, and the offset is calulated using
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// prev NC panels spanning k dim + cur NC panel spaning pc loop
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// cur iteration + (NC - NC') spanning current kc0 (<= KC).
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//
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//Eg: Consider the following reordered buffer diagram:
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// t1 t2
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// | |
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// | |..NC..|
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// | | |
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// |.NC. |.NC. |NC'|NC"
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// pc=0-+-----+-----+---+--+
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// KC| | | | |
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// | 1 | 3 | 5 |
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// pc=KC-+-----+-----+---st-+
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// KC| | | | |
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// | 2 | 4 | 6 | 7|
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// pc=k=2KC-+-----+-----+---+--+
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// |jc=0 |jc=NC|jc=2NC|
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//
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// The numbers 1,2..6,7 denotes the order in which reordered
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// KCxNC blocks are stored in memory, ie: block 1 followed by 2
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// followed by 3, etc. Given two threads t1 and t2, and t2 needs
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// to acces point st in the reorder buffer to write the data:
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// The offset calulation logic will be:
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// jc_cur_loop = 2NC, jc_cur_loop_rem = NC', pc = KC,
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// n_sub_updated = NC, k = 2KC, kc0_updated = KC
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//
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// st = ( jc_cur_loop * k ) <traverse blocks 1,2,3,4>
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// + ( n_sub_updated * pc ) <traverse block 5>
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// + ( NC' * kc0_updated) <traverse block 6>
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( ( packb_s32_s8 )lcntx->packb_fun_ptr )
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(
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( ( ( int8_t* )b_reorder->storage.aligned_buffer ) +
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( jc_cur_loop * k_updated ) + ( n_sub_updated * pc ) +
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( jc_cur_loop_rem * kc0_updated ) ),
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pack_b_column_sum + jc,
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( ( ( int8_t* )b->storage.aligned_buffer ) +
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( rs_b * pc ) + jc * cs_b),
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rs_b, cs_b, nc0, kc0, &rs_b_reorder, &cs_b_reorder
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);
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}
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adjust_B_panel_reordered_jc( &jc, jc_cur_loop );
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}
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}
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b_reorder->rs = rs_b_reorder;
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b_reorder->cs = cs_b_reorder;
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b_reorder->mtag = REORDERED;
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}
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void reordera_mr6_s8s8s32o32
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(
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lpgemm_obj_t* a,
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lpgemm_obj_t* a_reorder,
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rntm_t* rntm,
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lpgemm_cntx_t* lcntx
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)
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{
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dim_t MC = lcntx->blksz.MC;
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dim_t KC = lcntx->blksz.KC;
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dim_t rs_a = a->rs;
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dim_t rs_a_reorder;
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dim_t cs_a_reorder;
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dim_t k = a->width;
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dim_t m = a->length;
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for ( dim_t pc = 0; pc < k; pc += KC )
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{
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dim_t kc0 = bli_min( ( k - pc ), KC );
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// kc0 needs to be a multiple of 4 so that it can be used with
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// vpdpbusd instruction. Padding is added in cases this
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// condition is not satisfied, and therefore the kc0 offsets
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// used for packed/reordered buffers needs to be updated.
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dim_t kc0_updated = make_multiple_of_n( kc0, 4 );
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for ( dim_t ic = 0; ic < m; ic += MC )
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{
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dim_t mc0 = bli_min( ( m - ic ), MC );
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( ( packa_s32_s8 )lcntx->packa_fun_ptr )
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(
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( ( ( int8_t* )a_reorder->storage.aligned_buffer ) + ( pc * m ) +
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( ic * kc0_updated ) ),
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( ( ( int8_t* )a->storage.aligned_buffer ) + ( rs_a * ic ) + pc ),
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rs_a, mc0, kc0, &rs_a_reorder, &cs_a_reorder
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);
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}
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}
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a_reorder->rs = rs_a_reorder;
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a_reorder->cs = cs_a_reorder;
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a_reorder->mtag = REORDERED;
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}
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