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6c112632a7
- Multi-Threaded int8 GEMM (Input - uint8_t, int8_t, Output - int32_t). AVX512_vnni based micro-kernel for int8 gemm. Paralellization supported along m and n dimensions. - Multi-Threaded B matrix reorder support for sgemm. Reordering B matrix is packing entire B matrix upfront before sgemm. It allows sgemm to take advantage of packed B matrix without incurring packing costs during runtime. - Makefile updates to addon make rules to compile avx512 code for selected files in addon folder. - CPU features query enhancements to check for AVX512_VNNI flag. - Bench for int8 gemm and sgemm with B matrix reorder. Supports performance mode for benchmarking and accuracy mode for testing code correctness. AMD-Internal: [CPUPL-2102] Change-Id: I8fb25f5c2fbd97d756f95b623332cb29e3b8d182
79 lines
3.2 KiB
C
79 lines
3.2 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LPGEMM_THRINFO_UTILS_H
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#define LPGEMM_THRINFO_UTILS_H
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// Parallelization only supported along jc and ic loops. Thus not reusing the
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// existing thrinfo tree logic, since a light-weight work id generation will
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// suffice. However the logic used for thread meta data generation, specific
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// to jc and ic loops is borrowed.
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BLIS_INLINE void lpgemm_gen_thrinfo
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(
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lpgemm_thrinfo_t* thread,
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thrinfo_t* thread_jc,
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thrinfo_t* thread_ic
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)
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{
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if ( thread == NULL )
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{
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// Set n_ways=1 to ensure ST behaviour when thread is not initialized.
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// This is the case when BLIS_ENABLE_OPENMP is not defined.
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bli_thrinfo_set_ocomm_id( 0, thread_jc );
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bli_thrinfo_set_n_way( 1, thread_jc );
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bli_thrinfo_set_work_id( 0, thread_jc );
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bli_thrinfo_set_ocomm_id( 0, thread_ic );
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bli_thrinfo_set_n_way( 1, thread_ic );
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bli_thrinfo_set_work_id( 0, thread_ic );
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}
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else
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{
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// Replicate the logic in bli_l3_sup_thrinfo_create_root for jc thrinfo.
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bli_thrinfo_set_ocomm_id( thread->tid, thread_jc );
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bli_thrinfo_set_n_way( thread->jc_ways, thread_jc );
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dim_t jc_work_id = thread->tid / thread->ic_ways;
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bli_thrinfo_set_work_id( jc_work_id, thread_jc );
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// Replicate the sub node creation logic in bli_thrinfo_sup_create_for_cntl
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// for ic thrinfo.
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dim_t ic_comm_id = thread->tid % thread->ic_ways;
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bli_thrinfo_set_ocomm_id( ic_comm_id, thread_ic );
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bli_thrinfo_set_n_way( thread->ic_ways, thread_ic );
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bli_thrinfo_set_work_id( ic_comm_id, thread_ic );
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}
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}
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#endif //LPGEMM_THRINFO_UTILS_H
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