Arnav Sharma 25e59fcbb9 DGEMV Optimizations for NO_TRANSPOSE Cases ...

- AVX512 specific DGEMV native kernels are added for Zen4/5
  architectures to handle the NO_TRANSPOSE cases and are independent of
  the AXPYF fused kernels.
- The following set of kernels biased towards the n-dimension perform
  beta scaling of y vector within the kernel itself and handle cases
  where n is less than 5:
    - bli_dgemv_n_zen_int_32x8n_avx512( ... )
    - bli_dgemv_n_zen_int_32x4n_avx512( ... )
    - bli_dgemv_n_zen_int_32x2n_avx512( ... )
    - bli_dgemv_n_zen_int_32x1n_avx512( ... )
- The bli_dgemv_n_zen_int_16mx8_avx512( ... ) is biased towards the
  m-dimension and for this kernel beta scaling is handled beforehand
  within the framework.
- Added unit-tests for the new kernels.
- AVX2 path for Zen/2/3 architectures still follows the old approach of
  using fused kernel, namely AXPYF, to perform the GEMV operation.

AMD-Internal: [CPUPL-5560]
Change-Id: I22bc2a865cd28b9cdcb383e17d1ff38bdd28de79

2024-12-12 10:26:50 -05:00

..

bli_gemv_avx2.c

DGEMV Optimizations for NO_TRANSPOSE Cases

2024-12-12 10:26:50 -05:00

bli_gemv_zen_int_4.c

Code cleanup: Miscellaneous fixes

2024-08-06 06:56:01 -04:00

bli_gemv_zen_ref.c

DGEMV Optimizations for Tiny Sizes

2024-08-05 12:19:42 +05:30

bli_her2_zen_int_4.c

Optimized dher2 implementation

2022-01-05 05:51:15 -06:00

bli_her_zen_int_amd.c

Code cleanup: No newline at end of file

2023-04-21 10:02:48 -04:00