blis/kernels at 99770558bb90102f95ad31286a4d95984b928948 - blis

amd/blis

mirror of https://github.com/amd/blis.git synced 2026-04-20 07:38:53 +00:00

Files

Vignesh Balasubramanian 99770558bb AVX512 optimizations for CGEMM(Native)

- Implemented the following AVX512 native
  computational kernels for CGEMM :
  Row-preferential    : 4x24
  Column-preferential : 24x4

- The implementations use a common set of macros,
  defined in a separate header. This is due to the
  fact that the implementations differ solely on
  the matrix chosen for load/broadcast operations.

- Added the associated AVX512 based packing kernels,
  packing 24xk and 4xk panels of input.

- Registered the column-preferential kernel(24x4) in
  ZEN4 and ZEN5 contexts. Further updated the cache-blocking
  parameters.

- Removed redundant BLIS object creation and its contingencies
  in the native micro-kernel testing interface(for complex types).
  Added the required unit-tests for memory and functionality
  checks of the new kernels.

AMD-Interal: [CPUPL-6498]
Change-Id: I520ff17dba4c2f9bc277bf33ba9ab4384408ffe1

2025-02-28 03:18:24 -05:00

armsve

Merge commit 'cfa3db3f' into amd-main

2024-07-08 06:09:11 -04:00

armv7a

Add explicit handling for beta == 0 in armsve sd and armv7a d gemm ukrs.

2021-09-29 16:43:38 -05:00

armv8a

Armv8 Trash New Bulk Kernels

2021-10-08 02:35:58 +09:00

bgq

Replaced use of bool_t type with C99 bool.