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b426f9e04e
Implemented and registered power9 dgemm ukernel. Details: - Implemented 12x6 dgemm microkernel for power9. This microkernel assumes that elements of B have been duplicated/broadcast during the packing step. The microkernel uses a column orientation for its microtile vector registers and thus implements column storage and general stride IO cases. (A row storage IO case via in-register transposition may be added at a future date.) It should be noted that we recommend using this microkernel with gcc and *not* xlc, as issues with the latter cropped up during development, including but not limited to slightly incompatible vector register mnemonics in the GNU extended inline assembly clobber list.
47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
#
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# config_registry
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#
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# Please refer to the BLIS wiki on configurations for information on the
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# syntax and semantics of this file [1].
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#
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# [1] https://github.com/flame/blis/wiki/ConfigurationHowTo
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#
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# Processor families.
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x86_64: intel64 amd64
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intel64: skx knl haswell sandybridge penryn generic
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amd64: zen2 zen excavator steamroller piledriver bulldozer generic
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# NOTE: ARM families will remain disabled until runtime hardware detection
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# logic is added to BLIS.
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#arm64: cortexa57 generic
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#arm32: cortexa15 cortexa9 generic
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# Intel architectures.
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skx: skx/skx/haswell/zen
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knl: knl/knl/haswell/zen
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haswell: haswell/haswell/zen
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sandybridge: sandybridge
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penryn: penryn
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# AMD architectures.
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zen2: zen2/zen2/zen/haswell
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zen: zen/zen/haswell
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excavator: excavator/piledriver
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steamroller: steamroller/piledriver
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piledriver: piledriver
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bulldozer: bulldozer
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# ARM architectures.
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thunderx2: thunderx2/armv8a
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cortexa57: cortexa57/armv8a
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cortexa53: cortexa53/armv8a
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cortexa15: cortexa15/armv7a
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cortexa9: cortexa9/armv7a
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# IBM architectures.
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power9: power9
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bgq: bgq
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# Generic architectures.
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generic: generic
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