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https://github.com/amd/blis.git
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b426f9e04e
Implemented and registered power9 dgemm ukernel. Details: - Implemented 12x6 dgemm microkernel for power9. This microkernel assumes that elements of B have been duplicated/broadcast during the packing step. The microkernel uses a column orientation for its microtile vector registers and thus implements column storage and general stride IO cases. (A row storage IO case via in-register transposition may be added at a future date.) It should be noted that we recommend using this microkernel with gcc and *not* xlc, as issues with the latter cropped up during development, including but not limited to slightly incompatible vector register mnemonics in the GNU extended inline assembly clobber list.
203 lines
5.2 KiB
C
203 lines
5.2 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018-2019, Advanced Micro Devices, Inc.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BLIS_CONFIGURETIME_CPUID
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#include "blis.h"
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#else
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#define BLIS_EXPORT_BLIS
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#include "bli_system.h"
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#include "bli_type_defs.h"
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#include "bli_arch.h"
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#include "bli_cpuid.h"
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#endif
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// -----------------------------------------------------------------------------
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// The arch_t id for the currently running hardware. We initialize to -1,
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// which will be overwritten upon calling bli_arch_set_id().
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static arch_t id = -1;
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arch_t bli_arch_query_id( void )
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{
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bli_arch_set_id_once();
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// Simply return the id that was previously cached.
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return id;
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}
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// -----------------------------------------------------------------------------
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// A pthread structure used in pthread_once(). pthread_once() is guaranteed to
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// execute exactly once among all threads that pass in this control object.
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static bli_pthread_once_t once_id = BLIS_PTHREAD_ONCE_INIT;
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void bli_arch_set_id_once( void )
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{
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#ifndef BLIS_CONFIGURETIME_CPUID
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bli_pthread_once( &once_id, bli_arch_set_id );
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#endif
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}
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// -----------------------------------------------------------------------------
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void bli_arch_set_id( void )
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{
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// Architecture families.
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#if defined BLIS_FAMILY_INTEL64 || \
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defined BLIS_FAMILY_AMD64 || \
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defined BLIS_FAMILY_X86_64 || \
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defined BLIS_FAMILY_ARM64 || \
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defined BLIS_FAMILY_ARM32
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id = bli_cpuid_query_id();
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#endif
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// Intel microarchitectures.
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#ifdef BLIS_FAMILY_SKX
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id = BLIS_ARCH_SKX;
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#endif
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#ifdef BLIS_FAMILY_KNL
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id = BLIS_ARCH_KNL;
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#endif
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#ifdef BLIS_FAMILY_KNC
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id = BLIS_ARCH_KNC;
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#endif
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#ifdef BLIS_FAMILY_HASWELL
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id = BLIS_ARCH_HASWELL;
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#endif
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#ifdef BLIS_FAMILY_SANDYBRIDGE
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id = BLIS_ARCH_SANDYBRIDGE;
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#endif
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#ifdef BLIS_FAMILY_PENRYN
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id = BLIS_ARCH_PENRYN;
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#endif
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// AMD microarchitectures.
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#ifdef BLIS_FAMILY_ZEN2
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id = BLIS_ARCH_ZEN2;
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#endif
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#ifdef BLIS_FAMILY_ZEN
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id = BLIS_ARCH_ZEN;
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#endif
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#ifdef BLIS_FAMILY_EXCAVATOR
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id = BLIS_ARCH_EXCAVATOR;
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#endif
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#ifdef BLIS_FAMILY_STEAMROLLER
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id = BLIS_ARCH_STEAMROLLER;
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#endif
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#ifdef BLIS_FAMILY_PILEDRIVER
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id = BLIS_ARCH_PILEDRIVER;
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#endif
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#ifdef BLIS_FAMILY_BULLDOZER
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id = BLIS_ARCH_BULLDOZER;
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#endif
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// ARM microarchitectures.
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#ifdef BLIS_FAMILY_THUNDERX2
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id = BLIS_ARCH_THUNDERX2;
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#endif
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#ifdef BLIS_FAMILY_CORTEXA57
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id = BLIS_ARCH_CORTEXA57;
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#endif
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#ifdef BLIS_FAMILY_CORTEXA53
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id = BLIS_ARCH_CORTEXA53;
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#endif
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#ifdef BLIS_FAMILY_CORTEXA15
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id = BLIS_ARCH_CORTEXA15;
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#endif
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#ifdef BLIS_FAMILY_CORTEXA9
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id = BLIS_ARCH_CORTEXA9;
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#endif
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// IBM microarchitectures.
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#ifdef BLIS_FAMILY_POWER9
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id = BLIS_ARCH_POWER9;
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#endif
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#ifdef BLIS_FAMILY_POWER7
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id = BLIS_ARCH_POWER7;
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#endif
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#ifdef BLIS_FAMILY_BGQ
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id = BLIS_ARCH_BGQ;
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#endif
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// Generic microarchitecture.
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#ifdef BLIS_FAMILY_GENERIC
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id = BLIS_ARCH_GENERIC;
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#endif
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//printf( "blis_arch_query_id(): id = %u\n", id );
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//exit(1);
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}
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// -----------------------------------------------------------------------------
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// NOTE: This string array must be kept up-to-date with the arch_t
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// enumeration that is typedef'ed in bli_type_defs.h. That is, the
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// index order of each string should correspond to the implied/assigned
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// enum value given to the corresponding BLIS_ARCH_ value.
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static char* config_name[ BLIS_NUM_ARCHS ] =
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{
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"skx",
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"knl",
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"knc",
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"haswell",
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"sandybridge",
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"penryn",
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"zen2",
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"zen",
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"excavator",
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"steamroller",
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"piledriver",
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"bulldozer",
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"thunderx2",
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"cortexa57",
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"cortexa53",
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"cortexa15",
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"cortexa9",
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"power9",
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"power7",
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"bgq",
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"generic"
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};
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char* bli_arch_string( arch_t id )
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{
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return config_name[ id ];
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}
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