blis/kernels at b4b0887ca457716fb194e24c9631e10fc7337e4a - blis

amd/blis

mirror of https://github.com/amd/blis.git synced 2026-04-19 23:28:52 +00:00

Files

Vignesh Balasubramanian b4b0887ca4 Additional optimizations to ZGEMM SUP and Tiny codepaths(ZEN4 and ZEN5)

- Added a set of AVX512 fringe kernels(using masked loads and
  stores) in order to avoid rerouting to the GEMV typed API
  interface(when m = 1). This ensures uniformity in performance
  across the main and fringe cases, when the calls are multithreaded.

- Further tuned the thresholds to decide between ZGEMM Tiny, Small
  SUP and Native paths for ZEN4 and ZEN5 architectures(in case
  of parallel execution). This would account for additional
  combinations of the input dimensions.

- Moved the call to Tiny-ZGEMM before the BLIS object creation,
  since this code-path operates on raw buffers.

- Added the necessary test-cases for functional and memory testing
  of the newly added kernels.

AMD-Internal: [CPUPL-6378][CPUPL-6661]
Change-Id: I9af73d1b6ef82b26503d4fc373111132aee3afd6

2025-04-23 00:56:58 -04:00

armsve

Merge commit 'cfa3db3f' into amd-main

2024-07-08 06:09:11 -04:00

armv7a

Add explicit handling for beta == 0 in armsve sd and armv7a d gemm ukrs.

2021-09-29 16:43:38 -05:00

armv8a

Armv8 Trash New Bulk Kernels

2021-10-08 02:35:58 +09:00

bgq

Replaced use of bool_t type with C99 bool.