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amd/blis
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mirror of https://github.com/amd/blis.git synced 2026-05-11 09:39:59 +00:00
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bc828f7f8e3ddb9f58af07edc0b935b21759fb0f
blis/kernels
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Kiran Varaganti bc828f7f8e Added new axpyv (single precision) microkernel where it performs 10 FMAs per loop- This gives better performance than all other implementations of axpyv
Change-Id: Ic4f0e4c67e367d67d0b24febcf34f81a70a39972
2017-03-03 14:45:35 +05:30
..
arm/3
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
armv7a/3
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
armv8a/3
Fixed missing cntx argument in ARMv8 microkernels.
2016-11-27 14:40:47 +01:00
bgq
Added 'restrict' to l1v/l1f code in 'kernels' dir.
2016-04-27 14:57:40 -05:00
c99/3
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
loongson3a/3
Use 64-bit intermediate variable for k for architectures that do 64-bit loads in case dim_t is 32-bit.
2016-07-22 13:44:37 -05:00
mic/3
Use 64-bit intermediate variable for k for architectures that do 64-bit loads in case dim_t is 32-bit.
2016-07-22 13:44:37 -05:00
nacl/pnacl
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
old/x86
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
power7/3
Implemented runtime contexts and reorganized code.
2016-04-11 17:21:28 -05:00
x86_64
Added new axpyv (single precision) microkernel where it performs 10 FMAs per loop- This gives better performance than all other implementations of axpyv
2017-03-03 14:45:35 +05:30
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