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https://github.com/amd/blis.git
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61584deddf
Details: - Added 512-bit specific 'a64fx' subconfiguration that uses empirically tuned block size by Stepan Nassyr. This subconfig also sets the sector cache size and enables memory-tagging code in SVE gemm kernels. This subconfig utilizes (16, k) and (10, k) DPACKM kernels. - Added a vector-length agnostic 'armsve' subconfiguration that computes blocksizes according to the analytical model. This part is ported from Stepan Nassyr's repository. - Implemented vector-length-agnostic [d/s/sh] gemm kernels for Arm SVE at size (2*VL, 10). These kernels use unindexed FMLA instructions because indexed FMLA takes 2 FMA units in many implementations. PS: There are indexed-FLMA kernels in Stepan Nassyr's repository. - Implemented 512-bit SVE dpackm kernels with in-register transpose support for sizes (16, k) and (10, k). - Extended 256-bit SVE dpackm kernels by Linaro Ltd. to 512-bit for size (12, k). This dpackm kernel is not currently used by any subconfiguration. - Implemented several experimental dgemmsup kernels which would improve performance in a few cases. However, those dgemmsup kernels generally underperform hence they are not currently used in any subconfig. - Note: This commit squashes several commits submitted by RuQing Xu via PR #424.
190 lines
6.6 KiB
C
190 lines
6.6 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2014, The University of Texas at Austin
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Copyright (C) 2018-2019, Advanced Micro Devices, Inc.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if 0
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// Used only during standalone testing of ARM support.
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#define FALSE 0
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#define TRUE 1
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typedef enum
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{
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BLIS_ARCH_CORTEXA57 = 10,
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BLIS_ARCH_CORTEXA15 = 11,
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BLIS_ARCH_CORTEXA9 = 12,
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BLIS_ARCH_GENERIC = 13
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} arch_t;
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typedef uint64_t bool;
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#define bli_abort abort
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#endif
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#ifndef BLIS_CPUID_H
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#define BLIS_CPUID_H
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arch_t bli_cpuid_query_id( void );
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// Intel
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bool bli_cpuid_is_skx( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_knl( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_haswell( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_sandybridge( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_penryn( uint32_t family, uint32_t model, uint32_t features );
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// AMD
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bool bli_cpuid_is_zen2( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_zen( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_excavator( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_steamroller( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_piledriver( uint32_t family, uint32_t model, uint32_t features );
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bool bli_cpuid_is_bulldozer( uint32_t family, uint32_t model, uint32_t features );
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// ARM
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bool bli_cpuid_is_thunderx2( uint32_t model, uint32_t part, uint32_t features );
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bool bli_cpuid_is_cortexa57( uint32_t model, uint32_t part, uint32_t features );
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bool bli_cpuid_is_cortexa53( uint32_t model, uint32_t part, uint32_t features );
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bool bli_cpuid_is_armsve( uint32_t model, uint32_t part, uint32_t features );
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bool bli_cpuid_is_a64fx( uint32_t model, uint32_t part, uint32_t features );
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bool bli_cpuid_is_cortexa15( uint32_t model, uint32_t part, uint32_t features );
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bool bli_cpuid_is_cortexa9( uint32_t model, uint32_t part, uint32_t features );
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uint32_t bli_cpuid_query( uint32_t* family, uint32_t* model, uint32_t* features );
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// -----------------------------------------------------------------------------
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//
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// This section of the file was based off of cpuid.hpp from TBLIS [1].
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//
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// [1] https://github.com/devinamatthews/tblis
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//
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/*
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Copyright (C) 2017, The University of Texas at Austin
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Copyright (C) 2017, Devin Matthews
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
|
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
|
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
|
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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BLIS_INLINE bool bli_cpuid_has_features( uint32_t have, uint32_t want )
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{
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return ( have & want ) == want;
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}
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// -----------------------------------------------------------------------------
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#if defined(__x86_64__) || defined(_M_X64) || defined(__i386) || defined(_M_IX86)
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// cpuid.h is now #included in bli_cpuid.c instead of here. See issue #393
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// for more information why this move was made.
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//#include "cpuid.h"
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void get_cpu_name( char *cpu_name );
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int vpu_count( void );
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enum
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{
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VENDOR_INTEL = 0,
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VENDOR_AMD,
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VENDOR_UNKNOWN
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};
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enum
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{
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FEATURE_SSE3 = 0x0001,
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FEATURE_SSSE3 = 0x0002,
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FEATURE_SSE41 = 0x0004,
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FEATURE_SSE42 = 0x0008,
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FEATURE_AVX = 0x0010,
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FEATURE_AVX2 = 0x0020,
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FEATURE_FMA3 = 0x0040,
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FEATURE_FMA4 = 0x0080,
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FEATURE_AVX512F = 0x0100,
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FEATURE_AVX512DQ = 0x0200,
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FEATURE_AVX512PF = 0x0400,
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FEATURE_AVX512ER = 0x0800,
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FEATURE_AVX512CD = 0x1000,
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FEATURE_AVX512BW = 0x2000,
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FEATURE_AVX512VL = 0x4000
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};
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#elif defined(__aarch64__) || defined(__arm__) || defined(_M_ARM)
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char* find_string_in( char* target, char* buffer, size_t buf_len, char* filepath );
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enum
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{
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VENDOR_ARM = 0,
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VENDOR_UNKNOWN
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};
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enum
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{
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MODEL_ARMV7 = 0,
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MODEL_ARMV8,
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MODEL_UNKNOWN
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};
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enum
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{
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FEATURE_NEON = 0x01,
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FEATURE_SVE = 0x02
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};
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#endif
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#endif
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