Aayush Kumar 8c537b0cd5 Added DTRSM Small Path AVX512 based LLNN/LUTN Variant Kernels ...

- 8x8 kernels are used for DTRSM SMALL
- Implemented fringe cases with below block sizes
   8x8, 8x4, 8x3, 8x2, 8x1
   4x8, 4x4, 4x3, 4x2, 4x1
   3x8, 3x4, 3x3, 3x2, 3x1
   2x8, 2x4, 2x3, 2x2, 2x1
   1x8, 1x4, 1x3, 1x2, 1x1

AMD-Internal: [CPUPL-2745]

Change-Id: I58d28912bddbaadb404052c0f3449ebbe3c97b68

2023-04-07 08:50:28 +00:00

..

0

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1d

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1f

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1m

Code cleanup: compiler warning fixes

2023-04-06 06:56:09 -04:00

2

ZGEMV var 2 bug fix

2023-04-05 01:31:24 -04:00

3

Implemented AVX-512 based 12x4 m-variant SUP kernels for ZGEMM

2023-04-06 04:49:15 -04:00

base

BLIS cpuid: better support Intel and future AMD processors

2023-04-06 11:29:33 -04:00

compat

Added DTRSM Small Path AVX512 based LLNN/LUTN Variant Kernels

2023-04-07 08:50:28 +00:00

include

Added DTRSM Small Path AVX512 based LLNN/LUTN Variant Kernels

2023-04-07 08:50:28 +00:00

ind

3m1 turning OFF

2021-05-26 10:06:54 +05:30

thread

Code cleanup and warnings fixes

2023-01-09 04:34:52 -05:00

util

BLIS cpuid tidy and bugfix.

2023-04-03 08:46:37 -04:00

CMakeLists.txt

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30