Meghana Vankadari cc98047fd6 Made framework changes to initialize specific cache block sizes for TRSM. ...

Details:
-This commit addresses the performance optimization(single-thread and
 multi-thread) for DTRSM on zen2.
-This new optimization employs different MC, KC & NC values for TRSM than
 what is being used in other Level-3 routines like DGEMM.
-Changed TRSM framework code to choose these blocksizes for TRSM
 on zen family configurations.
-Added a new field called "trsm_blkszs" to cntx structure in order to
 store TRSM specific block sizes.
-Implemented routines to initialize, set and query the TRSM-specific
 block sizes.
-Defined a new macro "AOCL_BLIS_ZEN" in configure script.
 This macro is automatically defined for zen family architectures.
 It enables us to choose different cache block sizes for TRSM instead of common level-3 block sizes.

Change-Id: Id8557b1c962a316b1edecca9cd582675eaf35fe6
Signed-off-by: Meghana Vankadari <meghana.vankadari@amd.com>
AMD-Internal: [CPUPL-656]

2020-03-09 10:33:42 +05:30

..

0

Use void_fp for function pointers instead of void*.

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1

Use void_fp for function pointers instead of void*.

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1d

Use void_fp for function pointers instead of void*.

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1f

Use void_fp for function pointers instead of void*.

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1m

Merge branch 'master' into amd

2019-10-11 11:53:51 -05:00

2

Use void_fp for function pointers instead of void*.

2019-08-23 14:18:08 +05:30

3

Made framework changes to initialize specific cache block sizes for TRSM.

2020-03-09 10:33:42 +05:30

base

Made framework changes to initialize specific cache block sizes for TRSM.

2020-03-09 10:33:42 +05:30

compat

Implemented gemm on skinny/unpacked matrices.

2019-08-23 14:18:08 +05:30

include

Made framework changes to initialize specific cache block sizes for TRSM.

2020-03-09 10:33:42 +05:30

ind

"Merge Selective Packing code from amd branch flame/blis"

2019-12-16 14:48:53 +05:30

thread

"Merge Selective Packing code from amd branch flame/blis"

2019-12-16 14:48:53 +05:30

util

Code review + tweaks to AMD's AOCL 2.0 PR (#349).

2019-10-11 10:24:24 -05:00