Meghana Vankadari 8557e2f7b9 Implemented GEMV for n=1 case using 32 YMM registers ...

Details:
- This implementation is picked form cntx when GEMM is invoked on
  machines that support AVX512 instructions by forcing the
  AVX2 path using AOCL_ENABLE_INSTRUCTIONS=AVX2 during run-time.
- This implementation uses MR=16 for GEMV.

AMD-Internal: [SWLCSG-3519]
Change-Id: I8598ce6b05c3d5a96c764d96089171570fbb9e1a

2025-05-05 05:31:13 -04:00

..

aocl_gemm

Implemented GEMV for n=1 case using 32 YMM registers

2025-05-05 05:31:13 -04:00

gemmd

Code cleanup: Copyright notices

2024-08-05 15:35:08 -04:00

CMakeLists.txt

Code cleanup: Copyright notices

2024-08-05 15:35:08 -04:00