Meghana Vankadari c9254bd9e9 Implemented LPGEMV(n=1) for AVX2-INT8 variants ...

- When n=1, reorder of B matrix is avoided to efficiently
  process data. A dot-product based kernel is implemented to
  perform gemv when n=1.

AMD-Internal: [SWLCSG-2354]
Change-Id: If5f74651ab11232d0b87d34bd05f65aacaea94f1

2024-06-18 12:09:18 +05:30

..

f32f32f32

SWISH post-op support for all LPGEMM APIs.

2024-05-06 06:05:11 -04:00

s8s8s16

SWISH post-op support for all LPGEMM APIs.

2024-05-06 06:05:11 -04:00

u8s8s16

Implemented LPGEMV(n=1) for AVX2-INT8 variants

2024-06-18 12:09:18 +05:30

gelu_avx2.h

Implemented ERF Based GeLU Activation for LPEGMM and SGEMM

2023-03-13 06:10:31 -04:00

lpgemm_util_l1_ops_avx2.c

aocl_softmax_f32 api's for softmax computation as part of lpgemm.

2023-04-21 05:26:08 -04:00

math_utils_avx2.h

Updated ERF threshold and packa changes in bf16

2023-10-29 23:55:46 +05:30

silu_avx2.h

SWISH post-op support for all LPGEMM APIs.

2024-05-06 06:05:11 -04:00