Harihara Sudhan S be7fb342c1 Added AVX512 based double and float SCALV ...

- Added AVX512 based double and float SCALV which will be used in
  Zen4 context.
- Added incx <= 0 check and alpha == 1 check to the BLAS layer of
  SSCAL.
- Modified BLAS framework of float SCAL to remove flag check and
  pick kernels based on architecture ID.
- AVX512 kernel is disabled for other Zen configurations using
  BLIS_KERNELS_ZEN4 macro.

AMD-Internal: [CPUPL-2766],[CPUPL-2765]
Change-Id: I4cdd93c9adbfbf8f7632730b8606ddcf70edd1dc

2023-04-11 14:41:56 +05:30

..

0

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1d

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1f

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30

1m

Code cleanup: compiler warning fixes

2023-04-06 06:56:09 -04:00

2

ZGEMV var 2 bug fix

2023-04-05 01:31:24 -04:00

3

Added SGEMM SUP blocksize override to zen4 context

2023-04-10 08:16:45 -04:00

base

BLIS cpuid: better support Intel and future AMD processors

2023-04-06 11:29:33 -04:00

compat

Added AVX512 based double and float SCALV

2023-04-11 14:41:56 +05:30

include

Added DTRSM Small Path AVX512 based LLNN/LUTN Variant Kernels

2023-04-07 08:50:28 +00:00

ind

3m1 turning OFF

2021-05-26 10:06:54 +05:30

thread

Code cleanup and warnings fixes

2023-01-09 04:34:52 -05:00

util

BLIS cpuid tidy and bugfix.

2023-04-03 08:46:37 -04:00

CMakeLists.txt

AOCL Windows: 3.1 BLIS changes

2021-03-08 19:04:17 +05:30