mirror of
https://github.com/amd/blis.git
synced 2026-05-25 10:54:33 +00:00
- This commit uses avx2 and avx512 masked load instructions for handling edge case where vector size is not exact multiple of avx2/avx512 vector register size. - Thanks to Shubham, Sharma <shubham.sharma3@amd.com> for avx512 ddotv kernel changes Change-Id: I998651eeb1083caf3308f1b45bd7d55b7974bcb4