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- Currently the BF16 kernels uses the AVX512 VNNI instructions. In order to support AVX2 kernels, the BF16 input has to be converted to F32 and then the F32 kernels has to be executed. - Added un-pack function for the B-Matrix, which does the unpacking of the Re-ordered BF16 B-Matrix and converts it to Float. - Added a kernel, to convert the matrix data from Bf16 to F32 for the give input. - Added a new path to the BF16 5LOOP to work with the BF16 data, where the packed/unpacked A matrix is converted from BF16 to F32. The packed B matrix is converted from BF16 to F32 and the re-ordered B matrix is unre-ordered and converted to F32 before feeding to the F32 micro kernels. - Removed AVX512 condition checks in BF16 code path. - Added the Re-order reference code path to support BF16 AVX2. - Currently the F32 AVX-2 kernels supports only F32 BIAS support. Added BF16 support for BIAS post-op in F32 AVX2 kernels. - Bug fix in the test input generation script. AMD Internal : [SWLCSG - 3281] Change-Id: I1f9d59bfae4d874bf9fdab9bcfec5da91eadb0fb
213 lines
5.2 KiB
C
213 lines
5.2 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BLIS_GEMM_BF16_PACKB
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#define BLIS_GEMM_BF16_PACKB
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#include "aocl_bf16_type.h"
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BLIS_INLINE dim_t get_packb_bf16bf16f32of32_min_NR()
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{
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// This is the minimum NR' required for use in bf16bf16f32 kernels. The idea
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// here is that since k needs to be a multiple of 2 (BF16 instr), NR'=16
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// results in total of 2 * NR' = 64 bytes to be loaded, which fits in 1 ZMM
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// register. Thus the smallest n fringe kernel dimension has n=16, and thus
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// any rounding for buffer sizes should be to 16.
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return 16;
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}
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typedef void (*pack_f32bf16)
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(
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bfloat16*,
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const float*,
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const dim_t,
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const dim_t,
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const dim_t,
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const dim_t,
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dim_t*,
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dim_t*
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);
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typedef void (*pack_s4bf16)
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(
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bfloat16 *,
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const int8_t *,
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const dim_t,
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const dim_t,
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dim_t *,
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dim_t *,
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lpgemm_pre_op_attr
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);
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typedef void (*pack_bf16)
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(
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bfloat16*,
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const bfloat16*,
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const dim_t,
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const dim_t,
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const dim_t,
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const dim_t,
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dim_t*,
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dim_t*
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);
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typedef void (*unpack_bf16)
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(
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const bfloat16*,
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bfloat16*,
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const dim_t,
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const dim_t,
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const dim_t,
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const dim_t
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);
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typedef void (*unpack_bf16f32)
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(
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const bfloat16*,
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float*,
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const dim_t,
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const dim_t,
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const dim_t,
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const dim_t
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);
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typedef void (*pack_s4)
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(
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int8_t*,
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const int8_t*,
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const dim_t,
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const dim_t,
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const dim_t,
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const dim_t,
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dim_t*,
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dim_t*,
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lpgemm_pre_op*,
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AOCL_MATRIX_TYPE
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);
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void packb_mxp_nr64_f32obf16
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(
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bfloat16 *pack_b_buffer_bf16bf16f32of32,
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const float *b,
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const dim_t rs_b,
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const dim_t cs_b,
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const dim_t NC,
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const dim_t KC,
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dim_t *rs_p,
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dim_t *cs_p
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);
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void packb_nr64_bf16bf16f32of32
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(
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bfloat16* pack_b_buffer_bf16bf16f32of32,
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const bfloat16* b,
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const dim_t rs_b,
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const dim_t cs_b,
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const dim_t NC,
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const dim_t KC,
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dim_t* rs_p,
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dim_t* cs_p
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);
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void packb_nr64_bf16s4f32of32
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(
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int8_t* pack_b_buffer,
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const int8_t* b,
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const dim_t rs_b,
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const dim_t cs_b,
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const dim_t NC,
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const dim_t KC,
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dim_t* rs_p,
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dim_t* cs_p,
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lpgemm_pre_op* pre_op,
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AOCL_MATRIX_TYPE mtag
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);
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void packsclb_nr64_bf16s4f32of32
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(
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bfloat16* packb_bf16,
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const int8_t* b,
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const dim_t NC,
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const dim_t KC,
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dim_t *rs_p,
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dim_t *cs_p,
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lpgemm_pre_op_attr pre_ops_attr
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);
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void packa_mr16_bf16bf16f32of32
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(
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bfloat16* pack_a_buffer,
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const bfloat16* a,
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const dim_t rs_a,
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const dim_t cs_a,
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const dim_t MC,
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const dim_t KC,
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dim_t* rs_p,
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dim_t* cs_p
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);
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void unpackb_nr64_bf16bf16f32of32
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(
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const bfloat16* unpack_b_buffer_bf16bf16f32of32,
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bfloat16* b,
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const dim_t NC,
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const dim_t KC,
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dim_t rs_b,
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dim_t cs_b
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);
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void unpackb_nr64_bf16_f32
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(
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const bfloat16* b,
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float* unpack_b_buffer,
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const dim_t NC,
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const dim_t KC,
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dim_t rs_b,
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dim_t cs_b
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);
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void cvt_pack_bf16_f32(
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float* pack_a_buffer,
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const bfloat16* a,
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const dim_t rs_a,
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const dim_t cs_a,
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const dim_t MC,
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const dim_t KC,
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dim_t* rs_p,
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dim_t* cs_p
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);
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#endif //BLIS_GEMM_BF16_PACKB
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