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-Currently only one eltwise post-op (one of relu/prelu/gelu_tanh/ gelu_erf) is supported in the post-op struct along with bias or downscale. This setup was sufficient when only activation functions were supported as eltwise post-ops. But with the introduction of clip post-op(a type of non-activation eltwise operation), it has become necessary to extend the post-ops framework to support multiple eltwise operations, with the multiple eltwise often used in the form activation eltwise op + non-activation eltwise ops. The aocl post-op struct is modified and the post-op parser is updated to support this use case. -The lpgemm_bench is updated to support testing/benchmarking of the multiple eltwise operations use case. The function for accuracy checking is modified to support correctness testing irrespective of the order and count of post-ops. Additionally the help message is updated so as to better describe the capabilities of lpgemm_bench. AMD-Internal: [CPUPL-3244] Change-Id: If4ce8d7261d32073da8fa4757ed4f2ea0e94249f
167 lines
4.8 KiB
C
167 lines
4.8 KiB
C
/*
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BLIS
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An object-based framework for developing high-performance BLAS-like
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libraries.
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Copyright (C) 2022-23, Advanced Micro Devices, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name(s) of the copyright holder(s) nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "blis.h"
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#include "lpgemm_post_ops.h"
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BLIS_INLINE void lpgemm_set_node_params
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(
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lpgemm_post_op* post_op_node,
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LPGEMM_POST_OP_CODE op_code,
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void* op1,
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void* op2,
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void* op3,
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void* scale_factor,
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bool is_power_of_2
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)
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{
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post_op_node->op_code = op_code;
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post_op_node->op_args1 = op1;
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post_op_node->op_args2 = op2;
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post_op_node->op_args3 = op3;
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post_op_node->scale_factor = scale_factor;
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post_op_node->is_power_of_2 = is_power_of_2;
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post_op_node->next = NULL;
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}
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void lpgemm_translate_to_post_ops_list
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(
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aocl_post_op* post_op_unparsed,
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lpgemm_post_op* post_op_list,
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void* scale_buffer,
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void* meta_arg
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)
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{
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if ( post_op_unparsed == NULL )
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{
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lpgemm_set_node_params
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(
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post_op_list, POST_OPS_DISABLE,
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NULL, NULL, NULL, NULL, FALSE
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);
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return;
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}
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if ( ( post_op_unparsed->seq_length > AOCL_MAX_POST_OPS ) )
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{
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lpgemm_set_node_params
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(
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post_op_list, POST_OPS_DISABLE,
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NULL, NULL, NULL, NULL, FALSE
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);
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return; //Error, seq length exceeds max post ops permitted.
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}
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dim_t e_i = 0; //Multiple eltwise supported.
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for ( dim_t i = 0; i < post_op_unparsed->seq_length; ++i )
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{
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// Dispatcher code
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switch ( *( post_op_unparsed->seq_vector + i ) )
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{
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case SUM:
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lpgemm_set_node_params
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(
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( post_op_list + i ), POST_OPS_SUM,
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post_op_unparsed->sum.buff,
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post_op_unparsed->sum.zero_point,
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NULL,
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post_op_unparsed->sum.scale_factor,
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post_op_unparsed->sum.is_power_of_2
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);
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break;
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case ELTWISE:
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{
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LPGEMM_POST_OP_CODE tmp_code = POST_OPS_DISABLE;
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// Eltwise algo dispatcher.
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switch ( ( post_op_unparsed->eltwise + e_i )->algo.algo_type )
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{
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case RELU:
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tmp_code = POST_OPS_RELU;
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break;
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case PRELU:
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tmp_code = POST_OPS_RELU_SCALE;
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break;
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case GELU_TANH:
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tmp_code = POST_OPS_GELU_TANH;
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break;
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case GELU_ERF:
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tmp_code = POST_OPS_GELU_ERF;
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break;
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case CLIP:
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tmp_code = POST_OPS_CLIP;
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break;
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default:
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break;
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}
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lpgemm_set_node_params
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(
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( post_op_list + i ), tmp_code,
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NULL,
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( post_op_unparsed->eltwise + e_i )->algo.alpha,
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( post_op_unparsed->eltwise + e_i )->algo.beta,
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( post_op_unparsed->eltwise + e_i )->scale_factor,
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( post_op_unparsed->eltwise + e_i )->is_power_of_2
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);
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e_i += 1;
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}
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break;
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case BIAS:
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lpgemm_set_node_params
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(
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( post_op_list + i ), POST_OPS_BIAS,
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post_op_unparsed->bias.bias,
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meta_arg, NULL, NULL, FALSE
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);
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break;
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case SCALE:
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lpgemm_set_node_params
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(
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( post_op_list + i ), POST_OPS_DOWNSCALE,
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post_op_unparsed->sum.zero_point,
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meta_arg, scale_buffer,
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post_op_unparsed->sum.scale_factor, FALSE
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);
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break;
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default:
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break;
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}
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// Simulating linked link using an array.
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if ( i < ( post_op_unparsed->seq_length - 1 ) )
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{
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( post_op_list + i )->next = ( post_op_list + i + 1);
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}
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}
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}
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