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* commit '81e10346': Alloc at least 1 elem in pool_t block_ptrs. (#560) Fix insufficient pool-growing logic in bli_pool.c. (#559) Arm SVE C/ZGEMM Fix FMOV 0 Mistake SH Kernel Unused Eigher Arm SVE C/ZGEMM Support *beta==0 Arm SVE Config armsve Use ZGEMM/CGEMM Arm SVE: Update Perf. Graph Arm SVE CGEMM 2Vx10 Unindex Process Alpha=1.0 Arm SVE ZGEMM 2Vx10 Unindex Process Alpha=1.0 A64FX Config Use ZGEMM/CGEMM Arm SVE Typo Fix ZGEMM/CGEMM C Prefetch Reg Arm SVE Add SGEMM 2Vx10 Unindexed Arm SVE ZGEMM Support Gather Load / Scatt. St. Arm SVE Add ZGEMM 2Vx10 Unindexed Arm SVE Add ZGEMM 2Vx7 Unindexed Arm SVE Add ZGEMM 2Vx8 Unindexed Update Travis CI badge Armv8 Trash New Bulk Kernels Enable testing 1m in `make check`. Config ArmSVE Unregister 12xk. Move 12xk to Old Revert __has_include(). Distinguish w/ BLIS_FAMILY_** Register firestorm into arm64 Metaconfig Armv8 DGEMMSUP Fix Edge 6x4 Switch Case Typo Armv8 DGEMMSUP Fix 8x4m Store Inst. Typo Add test for Apple M1 (firestorm) Firestorm CPUID Dispatcher Armv8 GEMMSUP Edge Cases Require Signed Ints Make error checking level a thread-local variable. Fix data race in testsuite. Update .appveyor.yml Firestorm Block Size Fixes Armv8 Handle *beta == 0 for GEMMSUP ??r Case. Move unused ARM SVE kernels to "old" directory. Add an option to control whether or not to use @rpath. Fix $ORIGIN usage on linux. Arm micro-architecture dispatch (#344) Use @path-based install name on MacOS and use relocatable RPATH entries for testsuite inaries. Armv8 Handle *beta == 0 for GEMMSUP ?rc Case. Armv8 Fix 6x8 Row-Maj Ukr Apply patch from @xrq-phys. Add explicit handling for beta == 0 in armsve sd and armv7a d gemm ukrs. bli_error: more cleanup on the error strings array Arm SVE Exclude SVE-Intrinsic Kernels for GCC 8-9 Arm SVE: Correct PACKM Ker Name: Intrinsic Kers Fix config_name in bli_arch.c Arm Whole GEMMSUP Call Route is Asm/Int Optimized Arm: DGEMMSUP `Macro' Edge Cases Stop Calling Ref Header Typo Arm: DGEMMSUP ??r(rv) Invoke Edge Size Arm: DGEMMSUP ?rc(rd) Invoke Edge Size Arm: Implement GEMMSUP Fallback Method Arm64 Fix: Support Alpha/Beta in GEMMSUP Intrin Added Apple Firestorm (A14/M1) Subconfig Arm64 8x4 Kernel Use Less Regs Armv8-A Supplimentary GEMMSUP Sizes for RD Armv8-A Fix GEMMSUP-RD Kernels on GNU Asm Armv8-A Adjust Types for PACKM Kernels Armv8-A GEMMSUP-RD 6x8m Armv8-A GEMMSUP-RD 6x8n Armv8-A s/d Packing Kernels Fix Typo Armv8-A Introduced s/d Packing Kernels Armv8-A DGEMMSUP 6x8m Kernel Armv8-A DGEMMSUP Adjustments Armv8-A Add More DGEMMSUP Armv8-A Add GEMMSUP 4x8n Kernel Armv8-A Add Part of GEMMSUP 8x4m Kernel Armv8A DGEMM 4x4 Kernel WIP. Slow Armv8-A Add 8x4 Kernel WIP AMD-Internal: [CPUPL-2698] Change-Id: I194ff69356740bb36ca189fd1bf9fef02eec3803
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53 lines
1.4 KiB
Plaintext
#
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# config_registry
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#
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# Please refer to the BLIS wiki on configurations for information on the
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# syntax and semantics of this file [1].
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#
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# [1] https://github.com/flame/blis/blob/master/docs/ConfigurationHowTo.md
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#
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# Processor families.
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x86_64: intel64 amdzen amd64_legacy
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intel64: skx knl haswell sandybridge penryn generic
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amd64_legacy: excavator steamroller piledriver bulldozer generic
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amdzen: zen5 zen4 zen3 zen2 zen generic
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arm64: firestorm thunderx2 cortexa57 cortexa53 generic
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arm32: cortexa15 cortexa9 generic
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# Intel architectures.
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skx: skx/skx/haswell/zen/zen4
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knl: knl/knl/haswell/zen
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haswell: haswell/haswell/zen
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sandybridge: sandybridge
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penryn: penryn
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# AMD architectures.
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zen5: zen5/zen5/zen4/skx/zen3/zen2/zen/haswell
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zen4: zen4/zen4/skx/zen3/zen2/zen/haswell
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zen3: zen3/zen3/zen2/zen/haswell
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zen2: zen2/zen2/zen/haswell
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zen: zen/zen/haswell
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excavator: excavator/piledriver
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steamroller: steamroller/piledriver
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piledriver: piledriver
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bulldozer: bulldozer
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# ARM architectures.
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armsve: armsve/armsve
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a64fx: a64fx/armsve
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firestorm: firestorm/armv8a
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thunderx2: thunderx2/armv8a
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cortexa57: cortexa57/armv8a
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cortexa53: cortexa53/armv8a
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cortexa15: cortexa15/armv7a
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cortexa9: cortexa9/armv7a
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# IBM architectures.
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power10: power10
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power9: power9
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bgq: bgq
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# Generic architectures.
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generic: generic
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