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[PR #411] feat: add SM90 FP8 x MXFP4 MegaMoE support #427
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📋 Pull Request Information
Original PR: https://github.com/deepseek-ai/DeepGEMM/pull/411
Author: @huangzhilin-hzl
Created: 8/20/2026
Status: 🔄 Open
Base:
nv_dev← Head:molou/sm90_humming_mxfp4afp8_megamoe_dev📝 Commits (3)
ec72c60feat(sm90): add FP8 x MXFP4 MegaMoE supportf026a32fix(sm90): harden cross-rank MegaMoE paths5d32216perf(sm90): integrate latest MXFP4 MegaMoE optimizations📊 Changes
20 files changed (+8479 additions, -60 deletions)
View changed files
➕
csrc/apis/sm90_mega.hpp(+429 -0)📝
csrc/jit/handle.hpp(+58 -6)📝
csrc/jit/kernel_runtime.hpp(+22 -12)➕
csrc/jit_kernels/heuristics/sm90_mega_moe.hpp(+138 -0)📝
csrc/jit_kernels/impls/runtime_utils.hpp(+6 -3)➕
csrc/jit_kernels/impls/sm90_fp8_mega_moe.hpp(+472 -0)📝
csrc/python_api.cpp(+2 -0)📝
deep_gemm/__init__.py(+5 -0)➕
deep_gemm/include/deep_gemm/impls/sm90_fp8_mega_moe.cuh(+4033 -0)📝
deep_gemm/include/deep_gemm/layout/mega_moe.cuh(+89 -5)➕
deep_gemm/include/deep_gemm/layout/sm90_mega_moe.cuh(+20 -0)📝
deep_gemm/include/deep_gemm/mma/sm90.cuh(+47 -0)📝
deep_gemm/include/deep_gemm/ptx/ld_st.cuh(+14 -0)📝
deep_gemm/include/deep_gemm/ptx/wgmma.cuh(+4 -0)📝
deep_gemm/include/deep_gemm/scheduler/mega_moe.cuh(+188 -34)📝
deep_gemm/mega/__init__.py(+252 -0)➕
deep_gemm/mega/mxfp4.py(+427 -0)➕
tests/bench_mega_moe_sm90.py(+672 -0)➕
tests/test_mega_moe_mxfp4_preprocess.py(+485 -0)➕
tests/test_mega_moe_sm90.py(+1116 -0)📄 Description
co-author: @guzekai01
Inspired by the SM90 FP8×FP8 MegaMoE implementation introduced in deepseek-ai/DeepGEMM#383 and the SM90 FP8×NVFP4 work in AichenF/DeepGEMM@megamoe_nvfp4_dev_m, this PR adds an optimized FP8×MXFP4 MegaMoE backend for SM90 GPUs. Keeping routed-expert weights in MXFP4 enables native reuse of Hugging Face MXFP4 MoE checkpoints, while substantially reducing GPU memory pressure by avoiding a persistent FP8 weight expansion.
Summary
Unified SM90 persistent execution.
Unlike #383, this implementation fuses dispatch, routed/shared L1 and L2, and combine into one persistent kernel. It adapts the SM100 ring-buffer and wave-interleaved scheduler to a cluster-free Hopper design using register-resident WGMMA, one CTA per task, and two resident CTAs per SM.
Humming-inspired MXFP4×FP8 compute path.
Routed weights remain packed MXFP4 in global memory. Model-load preprocessing rebases the K32 UE8M0 exponents into bounded relative scales plus one FP32 secondary scale per expert, following the fused MXFP4×FP8 approach used by Humming. During execution, packed E2M1 tiles are loaded into compact shared-memory staging, decoded and expanded on the fly into E4M3 FP8 tiles, and then consumed by Hopper WGMMA. This avoids materializing a persistent FP8 copy of the routed weights.
Benchmark Results
The benchmark follows the H20 workload shapes and timing methodology from #383. Results were collected on 8× NVIDIA H20 with
fast_math=1and cold-L2 measurements.vs PR #383is calculated asPR #383 / FP8×MXFP4 - 1;vs DeepEPis calculated asDeepEP / FP8×MXFP4 - 1. Positive values indicate that this implementation is faster.H20 High Throughput
H20 Low Latency
TODO
🔄 This issue represents a GitHub Pull Request. It cannot be merged through Gitea due to API limitations.