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[GH-ISSUE #111] 通过数据内存预处理可能会大幅提升性能 #64

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opened 2026-10-26 21:11:41 +00:00 by bsakaguchi · 6 comments
bsakaguchi commented 2026-10-26 21:11:41 +00:00
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Originally created by @fan-wenjie on GitHub (Jun 10, 2025).
Original GitHub issue: https://github.com/deepseek-ai/DeepGEMM/issues/111

在AMD2025推理优化挑战赛过程中发现的新方法，可大幅提升性能。
【关于矩阵乘法运算的一种新的实现方式-哔哩哔哩】
https://b23.tv/kOpd169
赛题第一题就是fp8-mm，是否有机器可以benchmark，另外可以加我GitHub名同名的微信，来私聊讨论优化。

Originally created by @fan-wenjie on GitHub (Jun 10, 2025). Original GitHub issue: https://github.com/deepseek-ai/DeepGEMM/issues/111 在AMD2025推理优化挑战赛过程中发现的新方法，可大幅提升性能。 【关于矩阵乘法运算的一种新的实现方式-哔哩哔哩】 https://b23.tv/kOpd169 赛题第一题就是fp8-mm，是否有机器可以benchmark，另外可以加我GitHub名同名的微信，来私聊讨论优化。
bsakaguchi commented 2026-10-26 21:11:43 +00:00
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@LyricZhao commented on GitHub (Jun 16, 2025):

不好意思，我理解您的优化更关注 AMD 的架构，我对 AMD 的指令集不太了解；对于 PTX ISA，如果您有优化的见解可以在这里留言~

<!-- gh-comment-id:2974940008 --> @LyricZhao commented on GitHub (Jun 16, 2025): 不好意思，我理解您的优化更关注 AMD 的架构，我对 AMD 的指令集不太了解；对于 PTX ISA，如果您有优化的见解可以在这里留言~
bsakaguchi commented 2026-10-26 21:11:43 +00:00
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@fan-wenjie commented on GitHub (Jun 17, 2025):

不好意思，我理解您的优化更关注 AMD 的架构，我对 AMD 的指令集不太了解；对于 PTX ISA，如果您有优化的见解可以在这里留言~

我这个不止针对AMD架构，甚至因为客观条件的限制我没计算卡。AMD给比赛排名靠前的人提供算力，我才有机会亲手实践自己的理论。这个是针对GPU SIMD的设计的通性优化的，我手上没nvidia的卡，但根据我对体系结构的认知，认为在nvidia的tensor core上此方法依然适用，只不过要调整顺序。您可以在B站和我私聊，也可以加我同名微信聊。

<!-- gh-comment-id:2979647342 --> @fan-wenjie commented on GitHub (Jun 17, 2025): > 不好意思，我理解您的优化更关注 AMD 的架构，我对 AMD 的指令集不太了解；对于 PTX ISA，如果您有优化的见解可以在这里留言~ 我这个不止针对AMD架构，甚至因为客观条件的限制我没计算卡。AMD给比赛排名靠前的人提供算力，我才有机会亲手实践自己的理论。这个是针对GPU SIMD的设计的通性优化的，我手上没nvidia的卡，但根据我对体系结构的认知，认为在nvidia的tensor core上此方法依然适用，只不过要调整顺序。您可以在B站和我私聊，也可以加我同名微信聊。
bsakaguchi commented 2026-10-26 21:11:44 +00:00
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@yiakwy-xpu-ml-framework-team commented on GitHub (Jun 30, 2025):

@fan-wenjie I have access to MI300X and H100 super machine. Could you clairfy your theory more clearly in fragment layout , I can help to evaluate it for you.

Note it is very unlikely you have created a pattern no one has tried before in NVIDIA data center chip (A100, H100/H200, B100/B200).

In NVIDIA data center chip, you can create pure registers based fragments for operands, but it is more common to create regsters based fragment for ACC and shared memory based fragment for operands. They also emphasis more on memory accesses pattern such as compute/IO overlap (WS, TMA usage), than workload balance (persistent kernel).

<!-- gh-comment-id:3018383475 --> @yiakwy-xpu-ml-framework-team commented on GitHub (Jun 30, 2025): @fan-wenjie I have access to MI300X and H100 super machine. Could you clairfy your theory more clearly in fragment layout , I can help to evaluate it for you. Note it is very unlikely you have created a pattern no one has tried before in NVIDIA data center chip (A100, H100/H200, B100/B200). In NVIDIA data center chip, you can create pure registers based fragments for operands, but it is more common to create regsters based fragment for ACC and shared memory based fragment for operands. They also emphasis more on memory accesses pattern such as compute/IO overlap (WS, TMA usage), than workload balance (persistent kernel).
bsakaguchi commented 2026-10-26 21:11:44 +00:00
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@fan-wenjie commented on GitHub (Jul 1, 2025):

不好意思，我理解您的优化更关注 AMD 的架构，我对 AMD 的指令集不太了解；对于 PTX ISA，如果您有优化的见解可以在这里留言~

@LyricZhao 要不内推我进ds，看看能否给我机会实现我的优化理论

<!-- gh-comment-id:3021525997 --> @fan-wenjie commented on GitHub (Jul 1, 2025): > 不好意思，我理解您的优化更关注 AMD 的架构，我对 AMD 的指令集不太了解；对于 PTX ISA，如果您有优化的见解可以在这里留言~ @LyricZhao 要不内推我进ds，看看能否给我机会实现我的优化理论
bsakaguchi commented 2026-10-26 21:11:45 +00:00
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@fan-wenjie commented on GitHub (Jul 2, 2025):

@fan-wenjie I have access to MI300X and H100 super machine. Could you clairfy your theory more clearly in fragment layout , I can help to evaluate it for you.

Note it is very unlikely you have created a pattern no one has tried before in NVIDIA data center chip (A100, H100/H200, B100/B200).

In NVIDIA data center chip, you can create pure registers based fragments for operands, but it is more common to create regsters based fragment for ACC and shared memory based fragment for operands. They also emphasis more on memory accesses pattern such as compute/IO overlap (WS, TMA usage), than workload balance (persistent kernel).

https://gitee.com/fanwenjie/reference-kernels/raw/main/problems/amd/fp8-mm/submission.py
here is the source on MI300X

<!-- gh-comment-id:3026151673 --> @fan-wenjie commented on GitHub (Jul 2, 2025): > [@fan-wenjie](https://github.com/fan-wenjie) I have access to MI300X and H100 super machine. Could you clairfy your theory more clearly in fragment layout , I can help to evaluate it for you. > > Note it is very unlikely you have created a pattern no one has tried before in NVIDIA data center chip (A100, H100/H200, B100/B200). > > In NVIDIA data center chip, you can create pure registers based fragments for operands, but it is more common to create regsters based fragment for ACC and shared memory based fragment for operands. They also emphasis more on memory accesses pattern such as compute/IO overlap (WS, TMA usage), than workload balance (persistent kernel). https://gitee.com/fanwenjie/reference-kernels/raw/main/problems/amd/fp8-mm/submission.py here is the source on MI300X
bsakaguchi commented 2026-10-26 21:11:45 +00:00
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@LyricZhao commented on GitHub (Jul 2, 2025):

要不内推我进ds，看看能否给我机会实现我的优化理论

不好意思，我仔细读了一下，在 NVIDIA GPU 上应该没有效果，这类优化在早期的架构可能是 work 的；现在的实现在 memory-bound 的 cases 下面已经可以打满 HBM 带宽了，没必要再预处理一下再浪费一整倍的时间；直接读大部分情况也可以打满，如果没打满一般说明实现有问题。

<!-- gh-comment-id:3026627554 --> @LyricZhao commented on GitHub (Jul 2, 2025): > 要不内推我进ds，看看能否给我机会实现我的优化理论 不好意思，我仔细读了一下，在 NVIDIA GPU 上应该没有效果，这类优化在早期的架构可能是 work 的；现在的实现在 memory-bound 的 cases 下面已经可以打满 HBM 带宽了，没必要再预处理一下再浪费一整倍的时间；直接读大部分情况也可以打满，如果没打满一般说明实现有问题。
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