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[GH-ISSUE #148] [Question] Why sm100 does not support block_m == 64 ? #86

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opened 2026-10-26 21:12:10 +00:00 by bsakaguchi · 3 comments
bsakaguchi commented 2026-10-26 21:12:10 +00:00
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Originally created by @simple86 on GitHub (Jul 31, 2025).
Original GitHub issue: https://github.com/deepseek-ai/DeepGEMM/issues/148

Why sm100 does not support block_m == 64?
Since UMMA instruction supports M == 64, what's the main constrain?
LAYOUT_AD_M is fixed as 128, can it support 64?

Originally created by @simple86 on GitHub (Jul 31, 2025). Original GitHub issue: https://github.com/deepseek-ai/DeepGEMM/issues/148 Why sm100 does not support `block_m == 64`? Since UMMA instruction supports `M == 64`, what's the main constrain? `LAYOUT_AD_M` is fixed as 128, can it support 64?
bsakaguchi commented 2026-10-26 21:12:11 +00:00
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@simple86 commented on GitHub (Jul 31, 2025):

Why sm100 does not support block_m == 64? Since UMMA instruction supports M == 64, what's the main constrain? LAYOUT_AD_M is fixed as 128, can it support 64?

cc @RayWang96

<!-- gh-comment-id:3138638955 --> @simple86 commented on GitHub (Jul 31, 2025): > Why sm100 does not support `block_m == 64`? Since UMMA instruction supports `M == 64`, what's the main constrain? `LAYOUT_AD_M` is fixed as 128, can it support 64? cc @RayWang96
bsakaguchi commented 2026-10-26 21:12:12 +00:00
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@RayWang96 commented on GitHub (Jul 31, 2025):

We are working on it, currently DeepGEMM only supports layout A&D, to support M == 64, we need to enable layout BF.

About layout, please refer to https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-data-path-layout-organization

<!-- gh-comment-id:3138672571 --> @RayWang96 commented on GitHub (Jul 31, 2025): We are working on it, currently DeepGEMM only supports layout A&D, to support M == 64, we need to enable layout BF. About layout, please refer to https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-data-path-layout-organization
bsakaguchi commented 2026-10-26 21:12:12 +00:00
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@simple86 commented on GitHub (Jul 31, 2025):

We are working on it, currently DeepGEMM only supports layout A&D, to support M == 64, we need to enable layout BF.

About layout, please refer to https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-data-path-layout-organization

Thanks!

<!-- gh-comment-id:3138794758 --> @simple86 commented on GitHub (Jul 31, 2025): > We are working on it, currently DeepGEMM only supports layout A&D, to support M == 64, we need to enable layout BF. > > About layout, please refer to https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-data-path-layout-organization Thanks!
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