From 12ae77b8cd48c52298fa26a812ba5c2b05a92eb5 Mon Sep 17 00:00:00 2001 From: Iwan Kawrakow Date: Mon, 25 Aug 2025 18:46:04 +0300 Subject: [PATCH] mmq_id: add iq3_kt, iq4_kt --- ggml/src/ggml-cuda/mmq_id.cu | 8 ++ ggml/src/ggml-cuda/mmq_id_common.cuh | 8 ++ .../mmq-instance-iq3_kt_id.cu | 91 +++++++++++++++++++ .../mmq-instance-iq4_kt_id.cu | 86 ++++++++++++++++++ 4 files changed, 193 insertions(+) create mode 100644 ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_kt_id.cu create mode 100644 ggml/src/ggml-cuda/template-instances/mmq-instance-iq4_kt_id.cu diff --git a/ggml/src/ggml-cuda/mmq_id.cu b/ggml/src/ggml-cuda/mmq_id.cu index 0cb3b5aa..230715c0 100644 --- a/ggml/src/ggml-cuda/mmq_id.cu +++ b/ggml/src/ggml-cuda/mmq_id.cu @@ -261,6 +261,12 @@ static void ggml_cuda_mul_mat_q_switch_type_id(ggml_backend_cuda_context & ctx, case GGML_TYPE_IQ2_KT: mul_mat_q_case_id(ctx, args, stream); break; + case GGML_TYPE_IQ3_KT: + mul_mat_q_case_id(ctx, args, stream); + break; + case GGML_TYPE_IQ4_KT: + mul_mat_q_case_id(ctx, args, stream); + break; default: GGML_ABORT("fatal error"); break; @@ -507,6 +513,8 @@ bool ggml_cuda_can_use_mmq_id(enum ggml_type type, int cc, int64_t ne11) { case GGML_TYPE_IQ6_K: case GGML_TYPE_IQ1_KT: case GGML_TYPE_IQ2_KT: + case GGML_TYPE_IQ3_KT: + case GGML_TYPE_IQ4_KT: mmq_supported = true; break; default: diff --git a/ggml/src/ggml-cuda/mmq_id_common.cuh b/ggml/src/ggml-cuda/mmq_id_common.cuh index 3329afa7..89baa31b 100644 --- a/ggml/src/ggml-cuda/mmq_id_common.cuh +++ b/ggml/src/ggml-cuda/mmq_id_common.cuh @@ -102,6 +102,8 @@ static mmq_q8_1_ds_layout mmq_get_q8_1_ds_layout(const ggml_type type_x) { case GGML_TYPE_IQ6_K: case GGML_TYPE_IQ1_KT: case GGML_TYPE_IQ2_KT: + case GGML_TYPE_IQ3_KT: + case GGML_TYPE_IQ4_KT: return MMQ_Q8_1_DS_LAYOUT_D4; default: GGML_ABORT("fatal error"); @@ -412,6 +414,8 @@ static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml case GGML_TYPE_IQ6_K : return MMQ_DP4A_TXS_Q8_0_16; case GGML_TYPE_IQ1_KT : return MMQ_DP4A_TXS_Q8_0; case GGML_TYPE_IQ2_KT : return MMQ_DP4A_TXS_Q8_0; + case GGML_TYPE_IQ3_KT : return MMQ_DP4A_TXS_Q8_0; + case GGML_TYPE_IQ4_KT : return MMQ_DP4A_TXS_Q8_0; default: return tile_x_sizes{0, 0, 0}; } } @@ -470,6 +474,8 @@ static constexpr __host__ __device__ int mmq_get_mma_tile_x_k(ggml_type type) { case GGML_TYPE_IQ6_K : return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_IQ1_KT : return MMQ_MMA_TILE_X_K_Q8_0; case GGML_TYPE_IQ2_KT : return MMQ_MMA_TILE_X_K_Q8_0; + case GGML_TYPE_IQ3_KT : return MMQ_MMA_TILE_X_K_Q8_0; + case GGML_TYPE_IQ4_KT : return MMQ_MMA_TILE_X_K_Q8_0; default: return 0; } } @@ -4171,5 +4177,7 @@ extern DECL_MMQ_CASE(GGML_TYPE_IQ5_K_R4); extern DECL_MMQ_CASE(GGML_TYPE_IQ6_K); extern DECL_MMQ_CASE(GGML_TYPE_IQ1_KT); extern DECL_MMQ_CASE(GGML_TYPE_IQ2_KT); +extern DECL_MMQ_CASE(GGML_TYPE_IQ3_KT); +extern DECL_MMQ_CASE(GGML_TYPE_IQ4_KT); // ------------------------------------------------------------------------------------------------------------------------- diff --git a/ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_kt_id.cu b/ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_kt_id.cu new file mode 100644 index 00000000..6af8b9d6 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_kt_id.cu @@ -0,0 +1,91 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmq_id_common.cuh" + +template static __device__ __forceinline__ void load_tiles_iq3_kt( + const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + + constexpr int nwarps = mmq_get_nwarps_device(); + + constexpr uint32_t ka = 0xCBAC1FED; + constexpr uint32_t km = 0x3f3f3f3f; + +#ifdef INT8_MMA_AVAILABLE + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + WARP_SIZE*2); +#else + constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_XS, mmq_y); + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + txs.qs); +#endif // INT8_MMA_AVAILABLE + + const int kqsx = threadIdx.x; + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { + int i = i0 + threadIdx.y; + + if (need_check) { + i = min(i, i_max); + } + + const block_iq3_kt * bxi = (const block_iq3_kt *)(x + i*stride + sizeof(float)) + kbx0; + + int ib32 = kqsx/4; + int j = kqsx%4; + const auto ql = (const uint16_t *)bxi->ql; + const auto qh = (const uint32_t *)bxi->qh; + uint32_t mask = 0x01010101 << ib32; + uint32_t val = ql[4*ib32+j] + 4096; + int2 v = {0, 0}; + for (int k = 0; k < 4; ++k) { + val *= ka; + v.x |= std::abs(ggml_cuda_dp4a(val & km, 0x01010101, -126)) << 8*k; + } + auto signs = __vcmpne4(qh[2*j+0] & mask, 0); + v.x = __vsub4(v.x ^ signs, signs); + for (int k = 0; k < 4; ++k) { + val *= ka; + v.y |= std::abs(ggml_cuda_dp4a(val & km, 0x01010101, -126)) << 8*k; + } + signs = __vcmpne4(qh[2*j+1] & mask, 0); + v.y = __vsub4(v.y ^ signs, signs); +#ifdef INT8_MMA_AVAILABLE + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*ib32 + 2*j + 0] = v.x; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*ib32 + 2*j + 1] = v.y; +#else + x_qs[i*(2*WARP_SIZE + 1) + 8*ib32 + 2*j + 0] = v.x; + x_qs[i*(2*WARP_SIZE + 1) + 8*ib32 + 2*j + 1] = v.y; +#endif // INT8_MMA_AVAILABLE + } + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 4) { + int i = i0 + threadIdx.y * 4 + threadIdx.x / (WARP_SIZE/4); + + if (need_check) { + i = min(i, i_max); + } + + const float * dptr = (const float *)(x + i*stride); + const float d = dptr[0] * 1.01f; + const block_iq3_kt * bxi = (const block_iq3_kt *)(dptr + 1) + kbx0; + int ib32 = threadIdx.x % 8; + const int ls = (bxi->scales[ib32%4] >> 4*(ib32/4)) & 0xf; + +#ifdef INT8_MMA_AVAILABLE + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = d * ls; +#else + x_df[i*(WARP_SIZE/4) + i/4 + threadIdx.x % 8] = d * ls; +#endif // INT8_MMA_AVAILABLE + } +} + +template +struct mmq_type_traits_id { + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_kt; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; +}; + +DECL_MMQ_CASE(GGML_TYPE_IQ3_KT); diff --git a/ggml/src/ggml-cuda/template-instances/mmq-instance-iq4_kt_id.cu b/ggml/src/ggml-cuda/template-instances/mmq-instance-iq4_kt_id.cu new file mode 100644 index 00000000..a27fe8a8 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/mmq-instance-iq4_kt_id.cu @@ -0,0 +1,86 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmq_id_common.cuh" + +template static __device__ __forceinline__ void load_tiles_iq4_kt( + const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + + constexpr int nwarps = mmq_get_nwarps_device(); + + constexpr uint32_t ka = 0xCBAC1FED; + constexpr uint32_t km = 0x3f3f3f3f; + +#ifdef INT8_MMA_AVAILABLE + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + WARP_SIZE*2); +#else + constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_XS, mmq_y); + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + txs.qs); +#endif // INT8_MMA_AVAILABLE + + const int kqsx = threadIdx.x; + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { + int i = i0 + threadIdx.y; + + if (need_check) { + i = min(i, i_max); + } + + const block_iq4_kt * bxi = (const block_iq4_kt *)(x + i*stride + sizeof(float)) + kbx0; + + int ib32 = kqsx/4; + int j = kqsx%4; + const auto shb = bxi->qs; + const auto ql = (const uint8_t *)(shb + 8); + const auto qh = ql + 64; + const uint32_t sh = shb[ib32] >> (8 + 6*j); + uint32_t offset = 4096 + ((shb[ib32] & 1) << 15); + uint32_t val1 = offset + ql[8*ib32+2*j+0] + ((qh[8*(ib32%4)+2*j+0] << (8 - 4*(ib32/4))) & 0xf00) + ((sh & 7) << 12); + uint32_t val2 = offset + ql[8*ib32+2*j+1] + ((qh[8*(ib32%4)+2*j+1] << (8 - 4*(ib32/4))) & 0xf00) + ((sh & 56) << 9); + int2 v = {0, 0}; + for (int k = 0; k < 4; ++k) { + val1 *= ka; + val2 *= ka; + v.x |= (ggml_cuda_dp4a(val1 & km, 0x01010101, -126) & 0xff) << 8*k; + v.y |= (ggml_cuda_dp4a(val2 & km, 0x01010101, -126) & 0xff) << 8*k; + } +#ifdef INT8_MMA_AVAILABLE + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*ib32 + 2*j + 0] = v.x; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + 8*ib32 + 2*j + 1] = v.y; +#else + x_qs[i*(2*WARP_SIZE + 1) + 8*ib32 + 2*j + 0] = v.x; + x_qs[i*(2*WARP_SIZE + 1) + 8*ib32 + 2*j + 1] = v.y; +#endif // INT8_MMA_AVAILABLE + } + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 4) { + int i = i0 + threadIdx.y * 4 + threadIdx.x / (WARP_SIZE/4); + + if (need_check) { + i = min(i, i_max); + } + + const float * dptr = (const float *)(x + i*stride); + const block_iq4_kt * bxi = (const block_iq4_kt *)(dptr + 1) + kbx0; + const int ls = (bxi->qs[threadIdx.x % 8] & 0xff) >> 1; + +#ifdef INT8_MMA_AVAILABLE + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = dptr[0] * (ls - 64); +#else + x_df[i*(WARP_SIZE/4) + i/4 + threadIdx.x % 8] = dptr[0] * (ls - 64); +#endif // INT8_MMA_AVAILABLE + } +} + +template +struct mmq_type_traits_id { + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_kt; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; +}; + +DECL_MMQ_CASE(GGML_TYPE_IQ4_KT);