diff --git a/ggml/src/ggml-cuda.cu b/ggml/src/ggml-cuda.cu index 7f4b01d4..de9816fe 100644 --- a/ggml/src/ggml-cuda.cu +++ b/ggml/src/ggml-cuda.cu @@ -3476,6 +3476,7 @@ GGML_CALL static bool ggml_backend_cuda_supports_op(ggml_backend_t backend, cons case GGML_TYPE_IQ4_KS_R4: case GGML_TYPE_IQ5_K_R4: case GGML_TYPE_IQ5_KS_R4: + case GGML_TYPE_IQ1_S_R4: return true; default: return false; diff --git a/ggml/src/ggml-cuda/convert.cu b/ggml/src/ggml-cuda/convert.cu index 644ee316..b2f77e09 100644 --- a/ggml/src/ggml-cuda/convert.cu +++ b/ggml/src/ggml-cuda/convert.cu @@ -526,6 +526,41 @@ static __global__ void dequantize_block_iq1_s(const void * __restrict__ vx, dst_ } } +template +static __global__ void dequantize_block_iq1_s_r4(const void * __restrict__ vx, dst_t * __restrict__ yy, int64_t n_per_row, int64_t row_size) { + + int64_t ii = blockIdx.x; + + int64_t nblock = n_per_row/32; + int64_t row = (8*ii)/nblock; + int64_t row4 = row/4; + int64_t ir = row%4; + int64_t ibl = (8*ii)%nblock; + + const int tid = threadIdx.x; + const int il = tid/8; // 0...3 + const int ib = tid%8; // 0...7 + + const half * dptr = (const half *)((const char *)vx + 4*row4*row_size); + const float d = (float)dptr[ir]; + const block_iq1_s_r4 * x = (const block_iq1_s_r4 *)(dptr + 4) + ibl; + dst_t * y = yy + 256*ii + 32*ib + 8*il; + + float dl = d*(2*((x[ib].qh[ir] >> 12) & 7) + 1); + float delta = dl * (x[ib].qh[ir] & 0x8000 ? -1-IQ1S_DELTA : -1+IQ1S_DELTA); + + uint32_t grid32[2]; const int8_t * q = (const int8_t *)grid32; + grid32[0] = iq1s_grid_gpu[x[ib].qs[4*il+ir] | (((x[ib].qh[ir] >> 3*il) & 7) << 8)]; + grid32[1] = (grid32[0] >> 4) & 0x0f0f0f0f; + grid32[0] &= 0x0f0f0f0f; + + if constexpr (std::is_same_v) { + for (int j = 0; j < 8; ++j) y[j] = __float2bfloat16(dl*q[j] + delta); + } else { + for (int j = 0; j < 8; ++j) y[j] = dl*q[j] + delta; + } +} + template static __global__ void dequantize_block_iq1_m(const void * __restrict__ vx, dst_t * __restrict__ yy) { @@ -1398,6 +1433,14 @@ static void dequantize_row_iq1_s_cuda(const void * vx, dst_t * y, const int64_t dequantize_block_iq1_s<<>>(vx, y); } +template +static void dequantize_row_iq1_s_r4_cuda(const void * vx, dst_t * y, const int64_t nrows, const int64_t n_per_row, cudaStream_t stream) { + const int64_t k = nrows * n_per_row; + const int64_t row_size = ggml_row_size(GGML_TYPE_IQ1_S_R4, n_per_row); + const int nb = (k + QK_K - 1) / QK_K; + dequantize_block_iq1_s_r4<<>>(vx, y, n_per_row, row_size); +} + template static void dequantize_row_iq4_nl_cuda(const void * vx, dst_t * y, const int64_t nrows, const int64_t n_per_row, cudaStream_t stream) { const int64_t k = nrows * n_per_row; @@ -1651,6 +1694,8 @@ to_bf16_cuda_t ggml_get_to_bf16_cuda(ggml_type type) { return dequantize_row_iq5_k_r4_cuda; case GGML_TYPE_IQ5_KS_R4: return dequantize_row_iq5_ks_r4_cuda; + case GGML_TYPE_IQ1_S_R4: + return dequantize_row_iq1_s_r4_cuda; default: return nullptr; } @@ -1699,6 +1744,8 @@ to_fp16_cuda_t ggml_get_to_fp16_cuda(ggml_type type) { return dequantize_row_iq3_xxs_cuda; case GGML_TYPE_IQ1_S: return dequantize_row_iq1_s_cuda; + case GGML_TYPE_IQ1_S_R4: + return dequantize_row_iq1_s_r4_cuda; case GGML_TYPE_IQ1_M: return dequantize_row_iq1_m_cuda; case GGML_TYPE_IQ1_BN: @@ -1790,6 +1837,8 @@ to_fp32_cuda_t ggml_get_to_fp32_cuda(ggml_type type) { return dequantize_row_iq3_xxs_cuda; case GGML_TYPE_IQ1_S: return dequantize_row_iq1_s_cuda; + case GGML_TYPE_IQ1_S_R4: + return dequantize_row_iq1_s_r4_cuda; case GGML_TYPE_IQ1_M: return dequantize_row_iq1_m_cuda; case GGML_TYPE_IQ1_BN: diff --git a/ggml/src/ggml-cuda/iqk_mmvq.cu b/ggml/src/ggml-cuda/iqk_mmvq.cu index ae11ae14..37f78745 100644 --- a/ggml/src/ggml-cuda/iqk_mmvq.cu +++ b/ggml/src/ggml-cuda/iqk_mmvq.cu @@ -50,6 +50,13 @@ struct ggml_cuda_type_traits { static constexpr int qi = QI5_XS; }; +template<> +struct ggml_cuda_type_traits { + static constexpr int qk = QK_K; + static constexpr int qr = QR4_XS; + static constexpr int qi = QI4_XS; +}; + // Reminder: // constexpr int qk = ggml_cuda_type_traits::qk; @@ -353,6 +360,39 @@ __device__ __forceinline__ void vec_dot_iq4_ks_r4_q8_1( } } +// TODO +__device__ __forceinline__ void vec_dot_iq1_s_r4_q8_1( + const void * __restrict__ vbq, const block_q8_1 * __restrict__ bq8_1, const int & kbx, const int & iqs, float * result) { + + *result = 0; return; + + const float * dptr = (const float *)vbq; + const block_iq4_ks_r4 * bq4 = (const block_iq4_ks_r4 *)(dptr + 4) + kbx; + + // iqs is 0...28 in steps of 2 + const int ib16 = iqs/2; + const float d8 = __low2float(bq8_1[ib16/2].ds); + const int32_t * q8 = (const int *)bq8_1[ib16/2].qs + 4*(ib16%2); + + int ib32 = ib16/2; + int is = ib16%2; + const uint32_t * scales32 = (const uint32_t *)bq4->scales; + int scales = __vsub4(scales32[ib32] & 0xfefefefe, 0x7f7f7f7f); + const int8_t * s8 = (const int8_t *)&scales; + int2 val; + const int * q4 = (const int *)bq4->qs + 16*ib32; + for (int i = 0; i < 4; ++i) { + auto values = iq4k_values + ((bq4->scales[4*ib32+i] & 1) << 4); + int sumi = 0; + val = get_int_from_table_16(q4[i+4*is+0], values); + sumi = ggml_cuda_dp4a(val.x, q8[0], ggml_cuda_dp4a(val.y, q8[2], sumi)); + val = get_int_from_table_16(q4[i+4*is+8], values); + sumi = ggml_cuda_dp4a(val.x, q8[1], ggml_cuda_dp4a(val.y, q8[3], sumi)); + const float d = dptr[i] * d8; + result[i] += d * sumi * s8[i]; + } +} + #define VDR_IQ4_KS_Q8_1_MMVQ 4 #define VDR_IQ4_KS_Q8_1_MMQ 4 @@ -1106,6 +1146,14 @@ void mul_mat_vec_iq4_ks_r4_q8_1_cuda( iqk_mul_mat_vec_q_cuda(vx, vy, dst, ids_data, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, ne2, nb02, nb12, nb2, ids_nb0, stream); } +void mul_mat_vec_iq1_s_r4_q8_1_cuda( + const void * vx, const void * vy, float * dst, const char * ids_data, + const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, + const int ne2, const uint64_t nb02, const uint64_t nb12, const uint64_t nb2, int64_t ids_nb0, cudaStream_t stream) { + + iqk_mul_mat_vec_q_cuda(vx, vy, dst, ids_data, ncols_x, nrows_x, nrows_y, ncols_y, nrows_dst, ne2, nb02, nb12, nb2, ids_nb0, stream); +} + void mul_mat_vec_iq5_k_r4_q8_1_cuda( const void * vx, const void * vy, float * dst, const char * ids_data, const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, diff --git a/ggml/src/ggml-cuda/iqk_mmvq.cuh b/ggml/src/ggml-cuda/iqk_mmvq.cuh index 5278ef1e..1e4257e8 100644 --- a/ggml/src/ggml-cuda/iqk_mmvq.cuh +++ b/ggml/src/ggml-cuda/iqk_mmvq.cuh @@ -90,3 +90,8 @@ void mul_mat_vec_iq5_ks_r4_q8_1_cuda( const void * vx, const void * vy, float * dst, const char * ids_data, const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, const int ne2, const uint64_t nb02, const uint64_t nb12, const uint64_t nb2, const int64_t ids_nb0, cudaStream_t stream); + +void mul_mat_vec_iq1_s_r4_q8_1_cuda( + const void * vx, const void * vy, float * dst, const char * ids_data, + const int ncols_x, const int nrows_x, const int nrows_y, const int ncols_y, const int nrows_dst, + const int ne2, const uint64_t nb02, const uint64_t nb12, const uint64_t nb2, const int64_t ids_nb0, cudaStream_t stream); diff --git a/ggml/src/ggml-cuda/mmvq.cu b/ggml/src/ggml-cuda/mmvq.cu index 6b5d37fa..cc00d278 100644 --- a/ggml/src/ggml-cuda/mmvq.cu +++ b/ggml/src/ggml-cuda/mmvq.cu @@ -560,6 +560,9 @@ static void ggml_cuda_op_mul_mat_vec_q_impl(ggml_backend_cuda_context & ctx, ggm case GGML_TYPE_IQ5_KS_R4: mul_mat_vec_iq5_ks_r4_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ids_data, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, ne2, nb02, nb12, nb2, ids_nb0, stream); break; + case GGML_TYPE_IQ1_S_R4: + mul_mat_vec_iq1_s_r4_q8_1_cuda(src0_dd_i, src1_ddq_i, dst_dd_i, ids_data, ne00, row_diff, src1_padded_row_size, src1_ncols, nrows_dst, ne2, nb02, nb12, nb2, ids_nb0, stream); + break; default: GGML_ABORT("fatal error"); break; @@ -679,6 +682,7 @@ bool ggml_cuda_mmvq_type_supported(ggml_type src0_type) { case GGML_TYPE_IQ4_KS_R4: case GGML_TYPE_IQ5_K_R4: case GGML_TYPE_IQ5_KS_R4: + case GGML_TYPE_IQ1_S_R4: return true; default: return false;