From e87a319f5f7950dc2e362b46d3f6fa5610cdfc5e Mon Sep 17 00:00:00 2001 From: Iwan Kawrakow Date: Wed, 25 Jun 2025 12:42:37 +0300 Subject: [PATCH] cuda: MMQ for iq3_k_r4 --- ggml/src/ggml-cuda/common.cuh | 22 +++++ ggml/src/ggml-cuda/iqk_mmvq.cu | 21 ----- ggml/src/ggml-cuda/mmq.cu | 4 + ggml/src/ggml-cuda/mmq.cuh | 4 + .../mmq-instance-iq3_k_r4.cu | 90 +++++++++++++++++++ 5 files changed, 120 insertions(+), 21 deletions(-) create mode 100644 ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_k_r4.cu diff --git a/ggml/src/ggml-cuda/common.cuh b/ggml/src/ggml-cuda/common.cuh index 3bf10a91..e2690cb3 100644 --- a/ggml/src/ggml-cuda/common.cuh +++ b/ggml/src/ggml-cuda/common.cuh @@ -669,6 +669,28 @@ struct ggml_cuda_type_traits { static constexpr int qi = QI4_XS; }; +template<> +struct ggml_cuda_type_traits { + static constexpr int qk = QK_K; + static constexpr int qr = QR4_XS; + static constexpr int qi = QI4_XS; +}; + +template<> +struct ggml_cuda_type_traits { + static constexpr int qk = QK_K; + static constexpr int qr = QR4_XS; + static constexpr int qi = QI4_XS; +}; + +template<> +struct ggml_cuda_type_traits { + static constexpr int qk = QK_K; + static constexpr int qr = QR5_XS; + static constexpr int qi = QI5_XS; +}; + + ////////////////////// struct ggml_cuda_device_info { diff --git a/ggml/src/ggml-cuda/iqk_mmvq.cu b/ggml/src/ggml-cuda/iqk_mmvq.cu index 776f768f..e69bcc4a 100644 --- a/ggml/src/ggml-cuda/iqk_mmvq.cu +++ b/ggml/src/ggml-cuda/iqk_mmvq.cu @@ -8,27 +8,6 @@ typedef void (*vec_dot_q_cuda_t)(const void * __restrict__ vbq, const block_q8_1 * __restrict__ bq8_1, const int & kbx, const int & iqs, float *); -template<> -struct ggml_cuda_type_traits { - static constexpr int qk = QK_K; - static constexpr int qr = QR4_XS; - static constexpr int qi = QI4_XS; -}; - -template<> -struct ggml_cuda_type_traits { - static constexpr int qk = QK_K; - static constexpr int qr = QR4_XS; - static constexpr int qi = QI4_XS; -}; - -template<> -struct ggml_cuda_type_traits { - static constexpr int qk = QK_K; - static constexpr int qr = QR5_XS; - static constexpr int qi = QI5_XS; -}; - template<> struct ggml_cuda_type_traits { static constexpr int qk = 32; diff --git a/ggml/src/ggml-cuda/mmq.cu b/ggml/src/ggml-cuda/mmq.cu index aa91233f..b1d94bea 100644 --- a/ggml/src/ggml-cuda/mmq.cu +++ b/ggml/src/ggml-cuda/mmq.cu @@ -136,6 +136,9 @@ void ggml_cuda_op_mul_mat_q( case GGML_TYPE_IQ2_K_R4: mul_mat_q_case(ctx, args, stream); break; + case GGML_TYPE_IQ3_K_R4: + mul_mat_q_case(ctx, args, stream); + break; default: GGML_ABORT("fatal error"); break; @@ -188,6 +191,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) { case GGML_TYPE_IQ3_KT: case GGML_TYPE_IQ4_KT: case GGML_TYPE_IQ2_K_R4: + case GGML_TYPE_IQ3_K_R4: mmq_supported = true; break; default: diff --git a/ggml/src/ggml-cuda/mmq.cuh b/ggml/src/ggml-cuda/mmq.cuh index 90f1a39c..a9d367ec 100644 --- a/ggml/src/ggml-cuda/mmq.cuh +++ b/ggml/src/ggml-cuda/mmq.cuh @@ -87,6 +87,7 @@ static mmq_q8_1_ds_layout mmq_get_q8_1_ds_layout(const ggml_type type_x) { case GGML_TYPE_IQ2_K: case GGML_TYPE_IQ2_K_R4: case GGML_TYPE_IQ3_K: + case GGML_TYPE_IQ3_K_R4: case GGML_TYPE_IQ4_KS: case GGML_TYPE_IQ4_KS_R4: case GGML_TYPE_IQ4_K: @@ -204,6 +205,7 @@ static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml case GGML_TYPE_IQ2_K : return MMQ_DP4A_TXS_Q8_0_16; case GGML_TYPE_IQ2_K_R4: return MMQ_DP4A_TXS_Q8_0_16; case GGML_TYPE_IQ3_K : return MMQ_DP4A_TXS_Q8_0_16; + case GGML_TYPE_IQ3_K_R4: return MMQ_DP4A_TXS_Q8_0_16; case GGML_TYPE_IQ4_K : return MMQ_DP4A_TXS_Q8_0_16; case GGML_TYPE_IQ5_K : return MMQ_DP4A_TXS_Q8_0_16; case GGML_TYPE_IQ6_K : return MMQ_DP4A_TXS_Q8_0_16; @@ -256,6 +258,7 @@ static constexpr __host__ __device__ int mmq_get_mma_tile_x_k(ggml_type type) { case GGML_TYPE_IQ2_K : return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_IQ2_K_R4: return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_IQ3_K : return MMQ_MMA_TILE_X_K_Q3_K; + case GGML_TYPE_IQ3_K_R4: return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_IQ4_K : return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_IQ5_K : return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_IQ6_K : return MMQ_MMA_TILE_X_K_Q3_K; @@ -4092,6 +4095,7 @@ extern DECL_MMQ_CASE(GGML_TYPE_IQ2_KS); extern DECL_MMQ_CASE(GGML_TYPE_IQ2_K); extern DECL_MMQ_CASE(GGML_TYPE_IQ2_K_R4); extern DECL_MMQ_CASE(GGML_TYPE_IQ3_K); +extern DECL_MMQ_CASE(GGML_TYPE_IQ3_K_R4); extern DECL_MMQ_CASE(GGML_TYPE_IQ4_K); extern DECL_MMQ_CASE(GGML_TYPE_IQ5_K); extern DECL_MMQ_CASE(GGML_TYPE_IQ5_KS); diff --git a/ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_k_r4.cu b/ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_k_r4.cu new file mode 100644 index 00000000..7b6096a3 --- /dev/null +++ b/ggml/src/ggml-cuda/template-instances/mmq-instance-iq3_k_r4.cu @@ -0,0 +1,90 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmq.cuh" + +template static __device__ __forceinline__ void load_tiles_iq3_k_r4( + const char * __restrict__ x, int * __restrict__ x_tile, const int & kbx0, const int & i_max, const int & stride) { + +#ifdef INT8_MMA_AVAILABLE + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + WARP_SIZE*2); +#else + constexpr tile_x_sizes txs = MMQ_DP4A_TXS_Q8_0_16; + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + txs.qs); +#endif // INT8_MMA_AVAILABLE + + const int kqsx = threadIdx.x/4; // 0...7 -> block of 32 + + uint32_t aux32[4]; + const uint8_t * aux8 = (const uint8_t *)aux32; +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += 4*nwarps) { + int i = i0 + 4*threadIdx.y + threadIdx.x%4; + + if (need_check) { + i = min(i, i_max); + } + int i4 = i/4; + int ir = i%4; + + const block_iq3_k_r4 * bxi = (const block_iq3_k_r4 *)(x + 4*i4*stride) + kbx0; + + const float d = __half2float(bxi->d[ir]); + + int qh = get_int_b4(bxi->qh, 4*kqsx+ir); + + #pragma unroll + for (int l = 0; l < 2; ++l) { + + auto values_l = iq3nl_values + (((bxi->extra[ir+4*l] >> kqsx) & 1) << 3); + + const int ql = get_int_b4(bxi->qs, 8*kqsx + ir + 4*l); + aux32[0] = ((ql >> 0) & 0x03030303) | ((qh << 2) & 0x04040404); + aux32[1] = ((ql >> 2) & 0x03030303) | ((qh << 1) & 0x04040404); + aux32[2] = ((ql >> 4) & 0x03030303) | ((qh >> 0) & 0x04040404); + aux32[3] = ((ql >> 6) & 0x03030303) | ((qh >> 1) & 0x04040404); + + const char4 val0 = make_char4(values_l[aux8[ 0]], values_l[aux8[ 1]], values_l[aux8[ 2]], values_l[aux8[ 3]]); + const char4 val1 = make_char4(values_l[aux8[ 4]], values_l[aux8[ 5]], values_l[aux8[ 6]], values_l[aux8[ 7]]); + const char4 val2 = make_char4(values_l[aux8[ 8]], values_l[aux8[ 9]], values_l[aux8[10]], values_l[aux8[11]]); + const char4 val3 = make_char4(values_l[aux8[12]], values_l[aux8[13]], values_l[aux8[14]], values_l[aux8[15]]); + +#ifdef INT8_MMA_AVAILABLE + x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + 4*l + 0] = *(const int *)&val0; + x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + 4*l + 1] = *(const int *)&val1; + x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + 4*l + 2] = *(const int *)&val2; + x_qs[i*MMQ_MMA_TILE_X_K_Q3_K + 8*kqsx + 4*l + 3] = *(const int *)&val3; +#else + x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + 4*l + 0] = *(const int *)&val0; + x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + 4*l + 1] = *(const int *)&val1; + x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + 4*l + 2] = *(const int *)&val2; + x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + 4*l + 3] = *(const int *)&val3; +#endif // INT8_MMA_AVAILABLE + + qh >>= 4; + } + + int is = 8*kqsx + ir; + float dl1 = d * (2*((bxi->scales_l[is%32] >> 4*(is/32)) & 0xf) + 1) * ((bxi->scales_h[is%8] >> (is/8)) & 1 ? -1 : 1); + is += 4; + float dl2 = d * (2*((bxi->scales_l[is%32] >> 4*(is/32)) & 0xf) + 1) * ((bxi->scales_h[is%8] >> (is/8)) & 1 ? -1 : 1); + +#ifdef INT8_MMA_AVAILABLE + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = dl1; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = dl2; +#else + x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = dl1; + x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = dl2; +#endif // INT8_MMA_AVAILABLE + } +} + +template +struct mmq_type_traits { + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_k_r4; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; +}; + +DECL_MMQ_CASE(GGML_TYPE_IQ3_K_R4);